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參數(shù)資料
| 型號(hào)： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 58/88頁(yè) |
| 文件大小： | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤(pán) |
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ADV7320/ADV7321
Rev. A | Page 61 of 88
HSYNC/VSYNC OUTPUT CONTROL
The ADV7320/ADV7321 have the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on
P_HSYNC/P_VSYNC, outputting the respective signals on the S_HSYNC and S_VSYNC pins.
Table 36. Hsync Output Control1
HD/ED2
Slave Mode
(0x10, Bit 2)
HD/ED Sync
Output Enable
(0x02, Bit 7)
SD Sync
Output Enable
(0x02, Bit 6)
I2C_Hsync_gen_sel
(0x14, Bit 1)
Signal on S_HSYNC Pin
Duration
x
0
x
Tristate
–
x
0
1
x
Pipelined SD Hsync
See Appendix 5—
External Hsync and
Vsync/Field Mode
1
x
0
External Pipelined HD/ED
Hsync
As per Hsync
timing
EAV/SAV Mode
1
x
0
Pipelined HD/ED Hsync based
on AV Code H bit
Same as line
blanking interval
x
1
x
1
Pipelined HD/ED Hsync
based on horizontal counter
Same as
embedded Hsync
1 In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.
2 ED = enhanced definition.
Table 37. Vsync Output Control1
HD/ED2
Slave Mode
(0x10, Bit 2)
HD/ED Sync
Output Enable
(0x02, Bit 7)
SD Sync
Output Enable
(0x02, Bit 6)
I2C_Vsync _gen_sel
(0x14, Bit 2)
Video Standard
Signal on
S_VSYNC Pin
Duration
x
0
x
Tristate
–
x
0
1
x
Interlaced
Pipelined SD
Vsync/field
See Appendix
External Hsync and
Vsync/Field Mode
1
x
0
x
External pipelined
HD/ED Vsync or
field signal
As per external
Vsync or field
signal
EAV/SAV Mode
1
x
0
All HD interlace
standards
External pipelined
field signal based
on AV Code F bit
Field
EAV/SAV Mode
1
x
0
All HD/ED
progressive
standards
Pipelined Vsync
based on AV
Code V bit
Vertical
blanking
interval
x
1
x
1
All HD/ED stan-
dards except
525p
External pipelined
HD/ED Vsync based
on vertical counter
Aligned with
serration lines
x
1
x
1
525p
External pipelined
HD/ED VSYNC
based on vertical
counter
Vertical
blanking
interval
1 In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.
2 ED = enhanced definition = progressive scan 525p or 625p.
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