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參數(shù)資料
| 型號： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 49/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 53 of 88
PROGRAMMABLE DAC GAIN CONTROL
DACs A, B, and C are controlled by Register 0A.
DACs D, E, and F are controlled by Register 0B.
The I2C control registers will adjust the output signal gain up or
down from its absolute level.
CASE B
700mV
300mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0A, 0x0B
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0A, 0x0B
700mV
300mV
05067-070
Figure 70. Programmable DAC Gain—Positive and Negative Gain
In Case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the signal
is increased from the reference signal.
In Case B, the video output signal is reduced. The absolute level
of the sync tip and blanking level both decrease with respect to
the reference video output signal. The overall gain of the signal
is reduced from the reference signal.
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC tune feature can change this output
current from 4.008 mA (7.5%) to 4.658 mA (+7.5%).
The reset value of the vid_out_ctrl registers is 0x00; therefore,
nominal DAC current is output. Table 33 is an example of how
the output current of the DACs varies for a nominal 4.33 mA
output current.
Table 33. DAC Gain Control
Reg 0x0A or 0x0B
DAC
Current
(mA)
% Gain
Note
0100 0000 (0x40)
4.658
7.5000%
0011 1111 (0x3F)
4.653
7.3820%
0011 1110 (0x3E)
4.648
7.3640%
...
0000 0010 (0x02)
4.43
0.0360%
0000 0001 (0x01)
4.38
0.0180%
0000 0000 (0x00)
4.33
0.0000%
(I2C Reset Value,
Nominal)
1111 1111 (0xFF)
4.25
0.0180%
1111 1110 (0xFE)
4.23
0.0360%
...
1100 0010 (0xC2)
4.018
7.3640%
1100 0001 (0xC1)
4.013
7.3820%
1100 0000 (0xC0)
4.008
7.5000%
GAMMA CORRECTION
[Subaddresses 0x24 to 0x37 for HD,
Subaddresses 0x66 to 0x79 for SD]
Gamma correction is available for SD and HD video. For each
standard, there are twenty 8-bit-wide registers. They are used to
program the Gamma Correction Curves A and B. HD Gamma
Curve A is programmed at Addresses 0x24 to 0x2D, and HD
Gamma Curve B is programmed at 0x2E to 0x7. SD Gamma
Curve A is programmed at Addresses 0x66 to 0x6F, and SD
Gamma Curve B is programmed at Addresses 0x70 to 0x79.
Generally gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied
wherever nonlinear processing is used.
Gamma correction uses the function
(
)γ
=
IN
OUT
Signal
where γ = gamma power factor.
Gamma correction is performed on the luma data only. The
user can choose either of two curves, Curve A or Curve B. At
any one time, only one of these curves can be used.
The response of the curve is programmed at 10 predefined
locations. In changing the values at these locations, the gamma
curve can be modified. Between these points, linear interpolation
is used to generate intermediate values. If the curve has a total
length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96,
128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed
and cannot be changed.
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