參數資料
| 型號： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 18/88頁 |
| 文件大小： | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 25 of 88
REGISTER ACCESS
The MPU can write to or read from all registers of the
ADV7320/ADV7321 except the subaddress registers, which are
write only registers. The subaddress register selected determines
which register the next read or write operation will access. All
communication with the part through the bus starts with an
access to the subaddress register. A read/write operation is then
performed from/to the target address, which increments to the
next address until a stop command is performed on the bus.
REGISTER PROGRAMMING
The following tables describe the functionality of each register.
All registers can be read from and written to, unless otherwise
stated.
SUBADDRESS REGISTER (SR7 TO SR0)
Each subaddress register is an 8-bit write only register. After the
encoder’s bus is accessed and a read or write operation is selected,
the subaddress is set up. The subaddress register determines to
or from which register the operation takes place.
Table 7. Registers 0x00 to 0x01
SR7–
SR0
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset Value
(Shaded)
0x00
0
Sleep mode off.
0xFC
Power
Mode
Register
Sleep Mode. With this
control enabled, the
current consumption is
reduced to μA level. All
DACs and the internal
PLL cct are disabled.
I2C registers can be
read from and written
to in sleep mode.
1
Sleep mode on.
0
PLL on.
PLL and Oversampling
Control. This control
allows the internal PLL
cct to be powered
down and the
oversampling to be
switched off.
1
PLL off.
DAC F: Power On/Off.
0
DAC F off.
1
DAC F on.
DAC E: Power On/Off.
0
DAC E off.
1
DAC E on.
DAC D: Power On/Off.
0
DAC D off.
1
DAC D on.
DAC C: Power On/Off.
0
DAC C off.
1
DAC C on.
DAC B: Power On/Off.
0
DAC B off.
1
DAC B on.
DAC A: Power On/Off.
0
DAC A off.
1
DAC A on.
0x01
Reserved.
0
Reserved.
Mode
Select
Register
Clock Edge.
0
Cb clocked upon
rising edge.
1
Y clocked upon rising
edge.
Only for PS
interleaved
input at 27
MHz.
Reserved.
0
Clock Align.
0
1
Must be set if the
phase delay between
the two input clocks is
<9.25 ns or >27.75 ns.
Only if two
input clocks
are used.
Input Mode.
0
SD input only.
0x38
0
1
PS input only.
0
1
0
HDTV input only.
0
1
SD and PS (20-bit).
1
0
SD and PS (10-bit).
1
0
1
SD and HDTV (SD
oversampled).
1
0
SD and HDTV (HDTV
oversampled).
1
PS only (at 54 MHz).
Y/C/S Bus Swap.
0
See Table 21.
1
Allows data to be
applied to data ports
in various
configurations (SD
feature only).
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