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參數(shù)資料
| 型號： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 59 of 88
FILTER C
FILTER B
FILTER A
FILTER D
FREQUENCY (Hz)
0
0.2
0.4
0.6
MAGNITUDE
0.8
1.0
05067-081
0
1
23
45
6
Figure 81. DNR Input Select
DNR MODE CONTROL
[Address 0x65, Bit 4]
This bit is used to select the DNR mode. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using an extended SSAF filter).
BLOCK OFFSET CONTROL
[Address 0x65, Bits 7 to 4]
Four bits are assigned to this control, which allows a maximum
shift of 15 pixels in a data block. Consider the fixed coring gain
positions. The block offset shifts the data in steps of one pixel
such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
SD ACTIVE VIDEO EDGE
[Subaddress 0x42, Bit 7]
When the active video edge feature is enabled, the first three
pixels and the last three pixels of the active video on the luma
channel are scaled so that maximum transitions on these pixels
are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8.
All other active video passes through unprocessed.
SAV/EAV STEP-EDGE CONTROL
The ADV7320/ADV7321 have the capability of controlling fast
rising and falling signals at the start and end of active video to
minimize ringing.
An algorithm monitors SAV and EAV and determines when the
edges are rising or falling too fast. The result is reduced ringing
at the start and end of active video for fast transitions.
Subaddress 0x42, Bit 7 = 1, enables this feature.
100 IRE
0 IRE
100 IRE
12.5 IRE
87.5 IRE
0 IRE
50 IRE
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
05067-082
Figure 82. Example of Active Video Edge Functionality
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