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參數(shù)資料
| 型號(hào)： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 38 of 88
INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be set
to 1:
Address 0x13, Bit 2 (HD 10-bit enable)
Address 0x48, Bit 4 (SD 10-bit enable)
Note that the ADV7320 defaults to simultaneous SD and PS
upon power-up (Address[0x01]: Input Mode = 011).
SD ONLY
Address[0x01]: Input Mode = 000
In 8-/10-bit input mode, multiplexed data is input on Pins S9 to
S0 (or Pins Y9 to Y0, depending on Register Address 0x01, Bit
7), with S0 being the LSB in 10-bit input mode (see Table 21).
Input standards supported are ITU-R BT.601/656. In 16-/20-bit
input mode, the Y pixel data is input on Pins S9 to S2 and CrCb
data is input on Pins Y9 to Y2 (see Table 21).
16-/20-Bit Mode Operation
When Register 0x01 Bit 7 = 0, CrCb data is input on the Y bus
and Y data is input on the S bus. When Register 0x01 Bit 7 = 1,
CrCb data is input on the C bus, and Y data is input on Y bus.
The 27 MHz clock input must be input on Pin CLKIN_A. Input
sync signals are input on the S_VSYNC, S_HSYNC, and
S_BLANK pins.
Table 21. SD 8-/10-Bit and 16-/20-Bit Configuration
Configuration
Parameter
8-/10-Bit Mode
16-/20-Bit Mode
Register 0x01, Bit 7 = 0
Y Bus
CrCb
S Bus
656/601, YCrCb
Y
C Bus
Register 0x01, Bit 7 = 1
Y Bus
656/601, YCrCb
Y
S Bus
C Bus
CrCb
MPEG2
DECODER
CLKIN_A
S[9:0] OR Y[9:0]*
27MHz
3
10
YCrCb
ADV7320/
ADV7321
*SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21.
05067-025
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 49. SD Only Input Mode
PS ONLY OR HDTV ONLY
Address[0x01]: Input Mode = 001 or 010, Respectively
YCrCb PS, HDTV, or any other HD YCrCb data can be input in
4:2:2 or 4:4:4. In 4:2:2 input format, the Y data is input on Pins
Y9 to Y0 and the CrCb data is input on Pins C9 to C0. In 4:4:4
input mode, Y data is input on Pins Y9 to Y0, Cb data is input on
Pins C9 to C0, and Cr data is input on Pins S9 to S0. If the
YCrCb data does not conform to SMPTE 293M (525p), ITU-R
BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p),
SMPTE 240M (1035i), or BTA-T1004/1362, the async timing
mode must be used. RGB data can only be input in 4:4:4
format in PS or HDTV input modes when HD RGB input is
enabled. G data is input on Pins Y9 to Y0, R data is input on
Pins S9 to S0, and B data is input on Pins C9 to C0. The clock
signal must be input on Pin CLKIN_A.
MPEG2
DECODER
CLKIN_A
C[9:0]
10
Cb
S[9:0]
Y[9:0]
INTERLACED TO
PROGRESSIVE
YCrCb
10
Cr
10
Y
3
27MHz
ADV7320/
ADV7321
05067-026
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 50. Progressive Scan Input Mode
SIMULTANEOUS SD/PS OR SD/HDTV
Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit),
Input Mode 101 (SD and HD, SD Oversampled), or Input
Mode 110 (SD and HD, HD Oversampled)
YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2
input format, the HD Y data is input on Pins Y9 to Y0 and the
HD CrCb data is input on Pins C9 to C0. If PS 4:2:2 data is
interleaved onto a single 10-bit bus, Pins Y9 to Y0 are used for
the input port. The input data is input at 27 MHz, with the data
being clocked upon the rising and falling edges of the input
clock. The input mode register at Address 0x01 is set
accordingly. If the YCrCb data does not conform to SMPTE
293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i),
SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004/1362,
the async timing mode must be used.
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