參數(shù)資料
型號(hào)： ADUC812BSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/57頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH 12BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
REV.
ADuC812
–16–
However, be sure to include the Schottky diodes shown in
Figure 8 (or at least the lower of the two diodes) to protect the
analog input from undervoltage conditions. To summarize this
section, use the circuit of Figure 8 to drive the analog input pins
of the ADuC812.
Voltage Reference Connections
The on-chip 2.5 V band gap voltage reference can be used as
the reference source for the ADC and DACs. To ensure the
accuracy of the voltage reference, decouple both the VREF pin and
the CREF pin to ground with 0.1 μF ceramic chip capacitors as
shown in Figure 9.
0.1 F
VREF
CREF
BUFFER
51
2.5V
BAND GAP
REFERENCE
ADuC812
BUFFER
Figure 9. Decoupling VREF and CREF
The internal voltage reference can also be tapped directly from
the VREF pin, if desired, to drive external circuitry. However, a
buffer must be used to ensure that no current is drawn from the
VREF pin itself. The voltage on the CREF pin is that of an internal
node within the buffer block, and its voltage is critical to ADC
and DAC accuracy. Do not connect anything to this pin except
the capacitor, and be sure to keep trace-lengths short on the
CREF capacitor, decoupling the node straight to the underlying
ground plane.
The ADuC812 powers up with its internal voltage reference in the
“off” state. The voltage reference turns on automatically whenever
the ADC or either DAC gets enabled in software. Once enabled,
the voltage reference requires approximately 65 ms to power up
and settle to its specified value. Be sure that your software allows
this time to elapse before initiating any conversions. If an external
voltage reference is preferred, connect it to the VREF pin as shown
in Figure 10 to overdrive the internal reference.
To ensure accurate ADC operation, the voltage applied to VREF
must be between 2.3 V and AVDD. In situations where analog
input signals are proportional to the power supply (such as some
strain gage applications), it may be desirable to connect the
VREF pin directly to AVDD. In such a configuration, the user
must also connect the CREF pin directly to AVDD to circumvent
internal buffer headroom limitations. This allows the ADC
input transfer function to span the full range of 0 V to AVDD
accurately.
Operation of the ADC or DACs with a reference voltage below
2.3 V, however, may incur loss of accuracy resulting in missing
codes or nonmonotonicity. For that reason, do not use a reference
voltage less than 2.3 V.
VDD
EXTERNAL
VOLTAGE
REFERENCE
VREF
CREF
BUFFER
51
2.5V
BAND GAP
REFERENCE
ADuC812
0.1 F
Figure 10. Using an External Voltage Reference
Configuring the ADC
The three SFRs (ADCCON1, ADCCON2, ADCCON3) con-
figure the ADC. In nearly all cases, an acquisition time of one
ADC clock (ADCCON1.2 = 0, ADCCON1.3 = 0) will provide
plenty of time for the ADuC812 to acquire its signal before
switching the internal track-and-hold amplifier into hold mode.
The only exception would be a high source impedance analog
input, but these should be buffered first anyway since source
impedances of greater than 610
Ω can cause dc errors as well.
The ADuC812’s successive approximation ADC is driven by a
divided down version of the master clock. To ensure adequate
ADC operation, this ADC clock must be between 400 kHz and
4 MHz, and optimum performance is obtained with ADC clock
between 400 kHz and 3 MHz. Frequencies within this range can
be achieved with master clock frequencies from 400 kHz to well
above 16 MHz with the four ADC clock divide ratios to choose
from. For example, with a 12 MHz master clock, set the ADC
clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz) by
setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1,
ADCCON1.4 = 0).
The total ADC conversion time is 15 ADC clocks, plus one
ADC clock for synchronization, plus the selected acquisition
time (1, 2, 3, or 4 ADC clocks). For the example above, with a
one clock acquisition time, total conversion time is 17 ADC clocks
(or 5.67 μs for a 3 MHz ADC clock).
In continuous conversion mode, a new conversion begins each
time the previous one finishes. The sample rate is the inverse of the
total conversion time described above. In the example above, the
continuous conversion mode sample rate would be 176.5 kHz.
ADC DMA Mode
The on-chip ADC has been designed to run at a maximum
conversion speed of 5 μs (200 kHz sampling rate). When con-
verting at this rate, the ADuC812 MicroConverter has 5 μs to
read the ADC result and store the result in memory for further
postprocessing, otherwise the next ADC sample could be lost.
In an interrupt driven routine, the MicroConverter would also
have to jump to the ADC Interrupt Service routine, which will
also increase the time required to store the ADC results. In
applications where the ADuC812 cannot sustain the interrupt
rate, an ADC DMA mode is provided.
To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set.
This allows the ADC results to be written directly to a 16 MByte
external static memory SRAM (mapped into data memory space)
F
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