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| 型號(hào)： | ADUC812BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 29/57頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 12BIT ADC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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REV.
ADuC812
–35–
UART SERIAL INTERFACE
The serial port is full-duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can begin
receiving a second byte before a previously received byte has been
read from the receive register. However, if the first byte still has
not been read by the time reception of the second byte is com-
plete, the first byte will be lost. The physical interface to the
serial data network is via Pins RXD(P3.0) and TXD(P3.1)
while the SFR interface to the UART is comprised of SBUF
and SCON, as described below.
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H). Writing to
SBUF loads the transmit register and reading SBUF accesses a
physically separate receive register.
UART Serial Port
SCON
Control Register
SFR Address
98H
Power-On Default Value
00H
Bit Addressable
Yes
0
M
S1
M
S2
M
SN
E
R8
B
T8
B
RI
TI
R
Table XIX. SCON SFR Bit Designations
Bit
Name
Description
7
SM0
UART Serial Mode Select Bits.
6
SM1
These bits select the Serial Port operating mode as follows:
SM0
SM1
Selected Operating Mode
0
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)
0
1
Mode 1: 8-bit UART, variable baud rate
1
0
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32)
1
Mode 3: 9-bit UART, variable baud rate
5
SM2
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is
cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is
set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will
be set as soon as the byte of data has been received.
4
REN
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
3
TB8
Serial Port Transmit (Bit 9).
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
2
RB8
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is
latched into RB8.
1
TI
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in
Modes 1, 2, and 3. TI must be cleared by user software.
0
RI
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in
Modes 1, 2, and 3. RI must be cleared by software.
F
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