參數(shù)資料
型號(hào)： ADUC812BSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/57頁(yè)
文件大小： 0K
描述： IC MCU FLASH 12BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
REV.
ADuC812
–40–
ADuC812 HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design consider-
ations that must be addressed when integrating the ADuC812
into any hardware system.
Clock Oscillator
The clock source for the ADuC812 can come either from an
external source or from the internal clock oscillator. To use the
internal clock oscillator, connect a parallel resonant crystal
between Pins 32 and 33, and connect a capacitor from each pin
to ground as shown below.
XTAL2
XTAL1
TO INTERNAL
TIMING CIRCUITS
ADuC812
Figure 35. External Parallel Resonant Crystal Connections
XTAL2
XTAL1
TO INTERNAL
TIMING CIRCUITS
ADuC812
EXTERNAL
CLOCK
SOURCE
Figure 36. Connecting an External Clock Source
Whether using the internal oscillator or an external clock source,
the ADuC812’s specified operational clock speed range is 300 kHz
to 16 MHz. The core is static, and will function all the way
down to dc. But at clock speeds slower that 400 kHz the ADC
will no longer function correctly. Therefore, to ensure specified
operation, use a clock frequency of at least 400 kHz and no
more than 16 MHz.
External Memory Interface
In addition to its internal program and data memories, the
ADuC812 can access up to 64 K bytes of external program
memory (ROM, PROM, etc.) and up to 16 M bytes of exter-
nal data memory (SRAM).
To select from which code space (internal or external program
memory) to begin executing instructions, tie the
EA (external
access) pin high or low, respectively. When
EA is high (pulled
up to VDD), user program execution will start at address 0 of the
internal 8 K bytes Flash/EE code space. When
EA is low (tied
to ground) user program execution will start at address 0 of the
external code space. In either case, addresses above 1FFFH
(8K) are mapped to the external space.
Note that a second very important function of the
EA pin is
described in the Single Pin Emulation Mode section.
External program memory (if used) must be connected to the
ADuC812 as illustrated in Figure 37. Note that 16 I/O lines
(Ports 0 and 2) are dedicated to bus functions during external
program memory fetches. Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the program counter
(PCL) as an address, and then goes into a float state awaiting
the arrival of the code byte from the program memory. During
the time that the low byte of the program counter is valid on P0,
the signal ALE (Address Latch Enable) clocks this byte into an
address latch. Meanwhile, Port 2 (P2) emits the high byte of the
program counter (PCH), then
PSEN strobes the EPROM and
the code byte is read into the ADuC812.
LATCH
EPROM
OE
A8–A15
A0–A7
D0–D7
(INSTRUCTION)
ADuC812
PSEN
P2
ALE
P0
Figure 37. External Program Memory Interface
Note that program memory addresses are always 16 bits wide, even
in cases where the actual amount of program memory used is less
than 64 K bytes. External program execution sacrifices two of the
8-bit ports (P0 and P2) to the function of addressing the program
memory. While executing from external program memory, Ports 0
and 2 can be used simultaneously for read/write access to external
data memory, but not for general-purpose I/O.
Though both external program memory and external data memory
are accessed by some of the same pins, the two are completely
independent of each other from a software point of view. For example,
the chip can read/write external data memory while executing
from external program memory.
Figure 38 shows a hardware configuration for accessing up to
64 K bytes of external RAM. This interface is standard to any
8051 compatible MCU.
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
ADuC812
RD
P2
ALE
P0
WE
WR
Figure 38. External Data Memory Interface
(64K Address Space)
F
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