參數(shù)資料
型號(hào)： ADUC812BSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/57頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH 12BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大小： 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
REV.
ADuC812
–22–
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 18. Details of the actual DAC
architecture can be found in U.S. Patent Number 5969657
(www.uspto.gov). Features of this architecture include inherent
guaranteed monotonicity and excellent differential linearity.
ADuC812
AVDD
VREF
R
OUTPUT
BUFFER
8
R
HIGH-Z
DISABLE
(FROM MCU)
Figure 18. Resistor String DAC Functional Equivalent
As illustrated in Figure 18, the reference source for each DAC is
user selectable in software. It can be either AVDD or VREF. In
0-to-AVDD mode, the DAC output transfer function spans from
0 V to the voltage at the AVDD pin. In 0-to-VREF mode, the
DAC output transfer function spans from 0 V to the internal
VREF, or if an external reference is applied, the voltage at the
VREF pin. The DAC output buffer amplifier features a true rail-to-
rail output stage implementation. This means that unloaded, each
output is capable of swinging to within less than 100 mV of both
AVDD and ground. Moreover, the DAC’s linearity specification
(when driving a 10 k
Ω resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 48, and, in
0-to-AVDD mode only, codes 3995 to 4095. Linearity degradation
near ground and VDD is caused by saturation of the output
amplifier, and a general representation of its effects (neglecting
offset and gain error) is illustrated in Figure 19. The dotted line
in Figure 19 indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output amplifier. Note
that Figure 19 represents a transfer function in 0-to-VDD mode
only. In 0-to-VREF mode (with VREF < VDD) the lower nonlinearity
would be similar, but the upper portion of the transfer function
would follow the “ideal” line right to the end (VREF in this case,
not VDD), showing no signs of endpoint linearity errors.
VDD
FFF HEX
000 HEX
VDD – 50mV
VDD – 100mV
100mV
50mV
0mV
Figure 19. Endpoint Nonlinearities Due to Amplifier
Saturation
The endpoint nonlinearities conceptually illustrated in Figure 19
get worse as a function of output loading. Most of the ADuC812’s
data sheet specifications assume a 10 k
Ω resistive load to ground
at the DAC output. As the output is forced to source or sink
more current, the nonlinear regions at the top or bottom
(respectively) of Figure 19 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figure 20 and Figure 21 illustrate this behavior. It should be noted
that the upper trace in each of these figures is only valid for an
output range selection of 0-to-AVDD. In 0-to-VREF mode, DAC
loading will not cause high-side voltage drops as long as the
reference voltage remains below the upper trace in the correspond-
ing figure. For example, if AVDD = 3 V and VREF = 2.5 V, the
high-side voltage will not be affected by loads less than 5 mA.
But somewhere around 7 mA the upper curve in Figure 21 drops
below 2.5 V (VREF), indicating that at these higher currents the
output will not be capable of reaching VREF.
SOURCE/SINK CURRENT – mA
5
05
10
15
OUTPUT
VOLTAGE
–
V
4
3
2
1
0
DAC LOADED WITH 0FFF HEX
DAC LOADED WITH 0000 HEX
Figure 20. Source and Sink Current Capability with
VREF = VDD = 5 V
F
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