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| 型號(hào)： | ADUC812BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 12BIT ADC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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REV.
ADuC812
–19–
Using the Flash/EE Program Memory
This 8K byte Flash/EE program memory array is mapped
into the lower 8K bytes of the 64K bytes program space address-
able by the ADuC812 and will be used to hold user code in
typical applications.
The program memory array can be programmed in one of
two modes:
Serial Downloading (In-Circuit Programming)
As part of its embedded download/debug kernel, the ADuC812
facilitates serial code download via the standard UART serial port.
Serial download mode is automatically entered on power-up if the
external pin
PSEN is pulled low through an external resistor as
shown in Figure 15. Once in this mode, the user can download code
to the program memory array while the device is sited in its target
application hardware. A PC serial download executable is provided
as part of the ADuC812 QuickStart development system.
The Serial Download protocol is detailed in a MicroConverter
Applications Note uC004, available from the ADI MicroConverter
website at www.analog.com/micronverter.
1k
PSEN
ADuC812
PULL
PSEN LOW DURING RESET TO
CONFIGURE THE ADuC812 FOR
SERIAL DOWNLOAD MODE
Figure 15. Flash/EE Memory Serial Download Mode
Programming
Parallel Programming
The parallel programming mode is fully compatible with
conventional third party Flash or EEPROM device programmers.
In this mode, Ports P0, P1, and P2 operate as the external data
and address bus interface, ALE operates as the Write Enable
strobe, and Port P3 is used as a general configuration port that
configures the device for various program and erase operations
during parallel programming.
The high voltage (12 V) supply required for Flash programming
is generated using on-chip charge pumps to supply the high
voltage program lines.
The complete parallel programming specification is available on the
MicroConverter homepage at www.analog.com/microconverter.
Using the Flash/EE Data Memory
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (Page 00H to Page 9FH) 4-byte pages,
as shown in Figure 16.
9FH
BYTE 1
BYTE 2
BYTE 3
BYTE 4
00H
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 16. User Flash/EE Memory Configuration
As with other ADuC812 user peripheral circuits, the interface to
this memory space is via a group of registers mapped in the SFR
space. A group of four data registers (EDATA1–4) is used to hold
the 4-byte page being accessed. EADRL is used to hold the 8-bit
address of the page being accessed. Finally, ECON is an
8-bit control register that may be written with one of five Flash/EE
memory access commands to trigger various read, write, erase,
and verify functions. These register can be summarized as follows:
ECON:
SFR Address
B9H
Function
Controls access to 640 bytes
Flash/EE data space.
Default
00H
EADRL:
SFR Address
C6H
Function
Holds the Flash/EE data
page address. 0H through 9FH
Default
00H
EDATA1–4:
SFR Address
BCH to BFH, respectively
Function
Holds the Flash/EE data
memory page write or page
read data bytes.
Default
EDATA1–4
00H
A block diagram of the SFR registered interface to the data
Flash/EE memory array is shown in Figure 17.
9FH
BYTE 1 BYTE 2 BYTE 3 BYTE 4
00H
EDATA1 (BYTE 1)
EDATA2 (BYTE 2)
EDATA3 (BYTE 3)
EDATA4 (BYTE 4)
EADRL
ECON COMMAND
INTERPRETER LOGIC
ECON
BYTE 1 BYTE 2 BYTE 3 BYTE 4
FUNCTION:
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
FUNCTION:
HOLDS COMMAND WORD
FUNCTION:
HOLDS THE 4-BYTE
PAGE WORD
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
Figure 17. User Flash/EE Memory Control and
Configuration
F
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