參數(shù)資料
型號： ADUC7021BCPZ62-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 80/92頁
文件大?。?/td> 0K
描述： IC MCU 12BIT 1MSPS UART 40-LFCSP
標(biāo)準(zhǔn)包裝： 750
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PLA，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 81 of 92
XMCFG Register
Name
Address
Default Value
Access
XMCFG
0xFFFFF000
0x00
R/W
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
XMxCON Registers
Name
Address
Default Value
Access
XM0CON
0xFFFFF010
0x00
R/W
XM1CON
0xFFFFF014
0x00
R/W
XM2CON
0xFFFFF018
0x00
R/W
XM3CON
0xFFFFF01C
0x00
R/W
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Table 81. XMxCON MMR Bit Descriptions
Bit
Description
1
Selects Data Bus Width. Set by the user to select a 16-bit
data bus. Cleared by the user to select an 8-bit data bus.
0
Enables Memory Region. Set by the user to enable memory
region. Cleared by the user to disable the memory region.
XMxPAR Registers
Name
Address
Default Value
Access
XM0PAR
0xFFFFF020
0x70FF
R/W
XM1PAR
0xFFFFF024
0x70FF
R/W
XM2PAR
0xFFFFF028
0x70FF
R/W
XM3PAR
0xFFFFF02C
0x70FF
R/W
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
Table 82. XMxPAR MMR Bit Descriptions
Bit
Description
15
Enable Byte Write Strobe. This bit is only used for two,
8-bit memory sharing the same memory region. Set by
the user to gate the A0 output with the WS output. This
allows byte write capability without using BHE and BLE
signals. Cleared by user to use BHE and BLE signals.
14:12
Number of Wait States on the Address Latch Enable Strobe.
11
Reserved.
10
Extra Address Hold Time. Set by the user to disable extra
hold time. Cleared by the user to enable one clock cycle
of hold on the address in read and write.
9
Extra Bus Transition Time on Read. Set by the user to disable
extra bus transition time. Cleared by the user to enable
one extra clock before and after the read strobe (RS).
8
Extra Bus Transition Time on Write. Set by the user to disable
extra bus transition time. Cleared by the user to enable
one extra clock before and after the write strobe (WS).
7:4
Number of Write Wait States. Select the number of wait
states added to the length of the WS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
3:0
Number of Read Wait States. Select the number of wait
states added to the length of the RS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
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