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參數(shù)資料
| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標準包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 38 of 92
ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to
1 MSPS when the clock source is 41.78 MHz. This block
provides the user with a multichannel multiplexer, a differential
track-and-hold, an on-chip reference, and an ADC.
The ADC consists of a 12-bit successive approximation
converter based around two capacitor DACs. Depending on the
input signal configuration, the ADC can operate in one of three
different modes:
Fully differential mode, for small and balanced signals
Single-ended mode, for any single-ended signals
Pseudo differential mode, for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input
The converter accepts an analog input range of 0 V to VREF when
operating in single-ended or pseudo differential mode. In fully
differential mode, the input signal must be balanced around a
common-mode voltage (VCM) in the 0 V to AVDD range with a
04
95
5-
01
1
AVDD
VCM
0
2VREF
Figure 37. Examples of Balanced Signals in Fully Differential Mode
A high precision, low drift, factory calibrated, 2.5 V reference is
provided on-chip. An external reference can also be connected as
described later in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in the
software. An external CONVSTART pin, an output generated from
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC channel
input. This facilitates an internal temperature sensor channel
that measures die temperature to an accuracy of ±3°C.
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range is
0 V to VREF. The output coding is straight binary in pseudo
differential and single-ended modes with
1 LSB = FS/4096, or
2.5 V/4096 = 0.61 mV, or
610 μV when VREF = 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 38.
04
95
5-
01
2
O
UT
P
UT
CO
DE
VOLTAGE INPUT
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
1LSB
0V
+FS – 1LSB
0000 0000 0010
0000 0000 0001
0000 0000 0000
1LSB =
FS
4096
Figure 38. ADC Transfer Function in Pseudo Differential or Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN– pins (that is, VIN+ – VIN–).
The maximum amplitude of the differential signal is therefore,
–VREF to +VREF p-p (that is, 2 × VREF). This is regardless of the
common mode (CM). The common mode is the average of the
two signals, for example, (VIN+ + VIN–)/2, and is therefore, the
voltage that the two inputs are centered on. This results in the
span of each input being CM ± VREF/2. This voltage has to be set
Analog Inputs section).
The output coding is twos complement in fully differential mode
with 1 LSB = 2 VREF/4096, or 2 × 2.5 V/4096 = 1.22 mV when
VREF = 2.5 V. The output result is ±11 bits, but this is shifted by
one to the right. This allows the result in ADCDAT to be declared
as a signed integer when writing C code. The designed code
transitions occur midway between successive integer LSB values
(that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS 3/2 LSB). The ideal
input/output transfer characteristic is shown in Figure 39.
04
95
5-
013
O
U
T
P
UT
CO
DE
VOLTAGE INPUT (VIN+ – VIN–)
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0010
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
–VREF + 1LSB
+VREF – 1LSB
0LSB
1LSB =
2 × VREF
4096
SIGN
BIT
Figure 39. ADC Transfer Function in Differential Mode
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