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參數(shù)資料
| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標準包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 57 of 92
Both switching edges are moved by an equal amount
(PWMDAT1 × tCORE) to preserve the symmetrical output
patterns.
Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA
register, which indicates whether operation is in the first or
second half cycle of the PWM period.
The resulting on-times of the PWM signals over the full PWM
period (two half periods) produced by the timing unit can be
written as follows:
On the high side
t0HH = PWMDAT0 + 2(PWMCH0 PWMDAT1) × tCORE
t0HL = PWMDAT0 2(PWMCH0 PWMDAT1) × tCORE
and the corresponding duty cycles (d)
d0H = t0HH/tS = + (PWMCH0 PWMDAT1)/PWMDAT0
and on the low side
t0LH = PWMDAT0 2(PWMCH0 + PWMDAT1)
× tCORE
t0LL = PWMDAT0 + 2(PWMCH0 + PWMDAT1)
× tCORE
and the corresponding duty cycles (d)
dOL = t0LH/tS = (PWMCH0 + PWMDAT1)/PWMDAT0
The minimum permissible t0H and t0L values are zero,
corresponding to a 0% duty cycle. In a similar fashion, the
maximum value is tS, corresponding to a 100% duty cycle.
Figure 59 shows the output signals from the timing unit for
operation in double update mode. It illustrates a general case
where the switching frequency, dead time, and duty cycle are all
changed in the second half of the PWM period. The same value
for any or all of these quantities can be used in both halves of the
PWM cycle. However, there is no guarantee that symmetrical
PWM signals are produced by the timing unit in double update
mode. Figure 59 also shows that the dead time inserted into the
PWM signals are done so in the same way as demonstrated in
single update mode.
0495
5-
029
–PWMDAT01/2
0H
0L
PWMSYNC
PWMSTA (0)
PWMDAT01
+PWMDAT01/2
–PWMDAT02/2
+PWMDAT02/2
PWMCH02
PWMCH01
2 × PWMDAT12
2 × PWMDAT11
PWMDAT22+1
PWMDAT21+1
00
PWMDAT02
Figure 59. Typical PWM Outputs of the 3-Phase Timing Unit
(Double Update Mode)
In general, the on-times of the PWM signals in double update
mode can be defined as follows:
On the high side
t0HH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 PWMDAT11 PWMDAT12) × tCORE
t0HL = (PWMDAT01
/2 + PWMDAT02/2 PWMCH01
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
where the subscript 1 refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (d) are
d0H = t0HH/tS = (PWMDAT01
/2 + PWMDAT02/2 +
PWMCH01 + PWMCH02 PWMDAT11 PWMDAT12)/
(PWMDAT01 + PWMDAT02)
On the low side
t0LH = (PWMDAT01/2 + PWMDAT02/2 + PWMCH01 +
PWMCH02 + PWMDAT11 + PWMDAT12) × tCORE
t0LL = (PWMDAT01
/2 + PWMDAT02/2 PWMCH01
PWMCH02 PWMDAT11 PWMDAT12) × tCORE
where the subscript 1 refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (d) are
d0L = t0LH/tS = (PWMDAT01/2 + PWMDAT02/2 +
PWMCH01 + PWMCH02 + PWMDAT11 +
PWMDAT12)/(PWMDAT01 + PWMDAT02)
For the completely general case in double update mode
(see Figure 59), the switching period is given by
tS = (PWMDAT01 + PWMDAT02) × tCORE
Again, the values of t0H and t0L are constrained to lie between
zero and tS.
PWM signals similar to those illustrated in Figure 58 and
Figure 59 can be produced on the 1H, 1L, 2H, and 2L outputs by
programming the PWMCH1 and PWMCH2 registers in a manner
identical to that described for PWMCH0. The PWM controller
does not produce any PWM outputs until all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers have been written
to at least once. Once these registers have been written, internal
counting of the timers in the 3-phase timing unit is enabled.
Writing to the PWMDAT0 register starts the internal timing of
the main PWM timer. Provided that the PWMDAT0 register is
written to prior to the PWMCH0, PWMCH1, and PWMCH2
registers in the initialization, the first PWMSYNC pulse and
interrupt (if enabled) appear 1.5 × tCORE × PWMDAT0 seconds
after the initial write to the PWMDAT0 register in single update
mode. In double update mode, the first PWMSYNC pulse
appears after PWMDAT0 × tCORE seconds.
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