參數(shù)資料
型號: ADUC7021BCPZ62-RL7
廠商: Analog Devices Inc
文件頁數(shù): 39/92頁
文件大?。?/td> 0K
描述: IC MCU 12BIT 1MSPS UART 40-LFCSP
標(biāo)準(zhǔn)包裝: 750
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 44MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: PLA,PWM,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 32
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 44 of 92
NONVOLATILE FLASH/EE MEMORY
The ADuC7019/20/21/22/24/25/26/27/28 incorporate Flash/EE
memory technology on-chip to provide the user with nonvolatile,
in-circuit reprogrammable memory space.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often
and more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC7019/20/21/22/24/25/26/27/28, Flash/EE memory
technology allows the user to update program code space in-
circuit, without the need to replace one-time programmable
(OTP) devices at remote operating nodes.
Each part contains a 64 kB array of Flash/EE memory. The
lower 62 kB is available to the user and the upper 2 kB contain
permanently embedded firmware, allowing in-circuit serial
download. These 2 kB of embedded firmware also contain a
power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as:
1.
Initial page erase sequence.
2.
Read/verify sequence (single Flash/EE).
3.
Byte program sequence memory.
4.
Second read/verify sequence (endurance cycle).
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of 40° to +125°C. The results
allow the specification of a minimum endurance figure over a
supply temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. In addition, note that
retention lifetime, based on an activation energy of 0.6 eV,
derates with TJ as shown in Figure 50.
150
300
450
600
30
40
55
70
85
100
125
135
150
RE
T
E
NT
IO
N
(
Y
ea
rs
)
0
04
95
5-
08
5
JUNCTION TEMPERATURE (°C)
Figure 50. Flash/EE Memory Data Retention
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the provided JTAG mode.
Serial Downloading (In-Circuit Programming)
The ADuC7019/20/21/22/24/25/26/27/28 facilitate code
download via the standard UART serial port or via the I2C port.
The parts enter serial download mode after a reset or power
cycle if the BM pin is pulled low through an external 1 kΩ
resistor. Once in serial download mode, the user can download
code to the full 62 kB of Flash/EE memory while the device is
in-circuit in its target application hardware. An executable PC
serial download is provided as part of the development system
for serial downloading via the UART. The AN-806 Application
Note describes the protocol for serial downloading via the
UART and I2C.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
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