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| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 50 of 92
Linearity degradation near ground and VDD is caused by satu-
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 53.
The dotted line in Figure 53 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 53 represents a transfer function
in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF modes
(with VREF < AVDD or DACREF < AVDD), the lower nonlinearity is
similar. However, the upper portion of the transfer function
follows the ideal line right to the end (VREF in this case, not AVDD),
showing no signs of endpoint linearity errors.
04
95
5-
0
24
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
Figure 53. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in
Figure 53 get worse as a function of output loading. Most
of the ADuC7019/20/21/22/24/25/26/27/28 data sheet
specifications assume a 5 kΩ resistive load to ground at the
DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom (respectively)
of Figure 53 become larger. With larger current demands, this
can significantly limit output voltage swing.
POWER SUPPLY MONITOR
The power supply monitor regulates the IOVDD supply on the
ADuC7019/20/21/22/24/25/26/27/28. It indicates when the
IOVDD supply pin drops below one of two supply trip points.
The monitor function is controlled via the PSMCON register.
If enabled in the IRQEN or FIQEN register, the monitor
interrupts the core using the PSMI bit in the PSMCON MMR.
This bit is immediately cleared once CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brown-out
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
PSMCON Register
Name
Address
Default Value
Access
PSMCON
0xFFFF0440
0x0008
R/W
Table 29. PSMCON MMR Bit Descriptions
Bit
Name
Description
3
CMP
Comparator Bit. This is a read-only bit that
directly reflects the state of the comparator.
Read 1 indicates the IOVDD supply is above its
selected trip point, or the PSM is in power-down
mode. Read 0 indicates the IOVDD supply is
below its selected trip point. This bit should be
set before leaving the interrupt service routine.
2
TP
Trip Point Selection Bits. 0 = 2.79 V, 1 = 3.07 V.
1
PSMEN
Power Supply Monitor Enable Bit. Set to 1 to
enable the power supply monitor circuit. Clear to
0 to disable the power supply monitor circuit.
0
PSMI
Power Supply Monitor Interrupt Bit. This bit is set
high by the MicroConverter once CMP goes low,
indicating low I/O supply. The PSMI bit can be
used to interrupt the processor. Once CMP
returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared once CMP goes high.
COMPARATOR
The ADuC7019/20/21/22/24/25/26/27/28 integrate voltage
comparators. The positive input is multiplexed with ADC2 and
the negative input has two options: ADC3 or DAC0. The output
of the comparator can be configured to generate a system
interrupt, be routed directly to the programmable logic array,
start an ADC conversion, or be on an external pin, CMPOUT, as
shown in Figure 54.
04
95
5-
025
MUX
IRQ
MUX
DAC0
ADC2/CMP0
ADC3/CMP1
P0.0/CMPOUT
Figure 54. Comparator
Note that because the ADuC7022, ADuC7025, and ADu7027
parts do not support a DAC0 output, it is not possible to use
DAC0 as a comparator input on these parts.
Hysteresis
Figure 55 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (VOS) is the difference
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(VH) is the width of the hysteresis range.
049
55
-06
3
CMPOUT
COMP0
VH
VOS
Figure 55. Comparator Hysteresis Transfer Function
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