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參數(shù)資料
| 型號(hào)： | AD9865CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 5/48頁(yè) |
| 文件大小： | 1672K |
| 代理商： | AD9865CHIPS |
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AD9865
Parameter
Rx PATH LATENCY
1
Full-Duplex Interface
Half-Duplex Interface
Rx PATH COMPOSITE AC PERFORMANCE @ f
ADC
= 50 MSPS
2
RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)
Signal-to-Noise and Distortion (SNR)
Total Harmonic Distortion (THD)
RxPGA Gain = 24 dB (Full-Scale =126 mV p-p)
Signal-to-Noise (SNR)
Total Harmonic Distortion (THD)
RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)
Signal-to-Noise and Distortion (SINAD)
Total Harmonic Distortion (THD)
Rx PATH COMPOSITE AC PERFORMANCE @ f
ADC
= 80 MSPS
3
RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)
Signal-to-Noise (SNR)
Total Harmonic Distortion (THD)
RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)
Signal-to-Noise (SNR)
Total Harmonic Distortion (THD)
RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)
Signal-to-Noise (SNR)
Total Harmonic Distortion (THD)
Rx-to-Tx PATH FULL-DUPLEX ISOLATION
(1 V p-p, 10 MHz Sine Wave Tx Output)
RxPGA Gain = 40 dB
IOUTP± Pins to RX± Pins
IOUTG± Pins to RX± Pins
RxPGA Gain = 0 dB
IOUTP± Pins to RX± Pins
IOUTG± Pins to RX± Pins
Rev. A | Page 5 of 48
Temp
Full
Full
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
Test Level
V
V
III
III
III
III
IV
IV
III
III
III
III
II
II
Min
58
58.9
Typ
10.5
10.0
43.7
71
59
67.2
59
66
41.8
67
58.6
62.9
59.6
69.7
Max
62.9
59.8
Unit
Cycles
Cycles
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
III
III
III
III
83
37
123
77
dBc
dBc
dBc
dBc
1
Includes RxPGA, ADC pipeline, and ADIO bus delay relative to f
ADC
.
2
f
IN
= 5 MHz, AIN = 1.0 dBFS , LPF cutoff frequency set to 15.5 MHz with Reg. 0x08 = 0x80.
3
f
IN
= 5 MHz, AIN = 1.0 dBFS , LPF cutoff frequency set to 26 MHz with Reg. 0x08 = 0x80.
POWER SUPPLY SPECIFICATIONS
AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V; R
SET
= 2 k, full-duplex operation with f
DATA
= 80 MSPS,
1
unless otherwise noted.
Table 3.
Parameter
SUPPLY VOLTAGES
AVDD
CLKVDD
DVDD
DRVDD
IS_TOTAL (Total Supply Current)
POWER CONSUMPTION
I
AVDD
+ I
CLKVDD
(Analog Supply Current)
I
DVDD
+ I
DRVDD
(Digital Supply Current)
Temp
Full
Full
Full
Full
Full
Full
Test Level
V
V
V
V
II
IV
IV
Min
3.135
3.0
3.0
3.0
Typ
3.3
3.3
3.3
3.3
406
311
95
Max
3.465
3.6
3.6
3.6
475
342
133
Unit
V
V
V
V
mA
mA
mA
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