參數(shù)資料
型號(hào)： AD9888
廠商： Analog Devices, Inc.
英文描述： 100/140/170/205 MSPS Analog Flat Panel Interface
中文描述： 100/140/170/205 MSPS的模擬平板顯示接口
文件頁(yè)數(shù)： 1/32頁(yè)
文件大?。?/td> 249K
代理商： AD9888
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD9888
Tel: 781/329-4700
Analog Devices, Inc., 2002
100/140/170/205 MSPS Analog
Flat Panel Interface
FUNCTIONAL BLOCK DIAGRAM
2:1
MUX
A/D
8
8
8
R
IN
R
IN
R
OUTA
R
OUTB
2:1
MUX
A/D
8
8
8
G
IN
G
IN
G
OUTA
G
OUTB
2:1
MUX
A/D
8
8
8
B
IN
B
IN
B
OUTA
B
OUTB
2:1
MUX
HSYNC
HSYNC
2:1
MUX
VSYNC
VSYNC
2:1
MUX
SOGIN
SOGIN
COAST
CLAMP
CKINV
CKEXT
FILT
SCL
SDA
A0
REF
BYPASS
DATACK
HSOUT
VSOUT
SOGOUT
SERIAL REGISTER
AND
POWER MANAGEMENT
REF
SYNC
PROCESSING
AND
CLOCK
GENERATION
CLAMP
CLAMP
CLAMP
AD9888
2
FEATURES
205 MSPS Maximum Conversion Rate
500 MHz Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
Less than 450 ps p-p PLL Clock Jitter @ 205 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for
“
Hot Plugging
”
2:1 Analog Input Mux
4:2:2 Output Format Mode
Midscale Clamping
Power-Down Mode
Low Power: <1 W Typical @ 205 MSPS
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
GENERAL DESCRIPTION
The AD9888 is a complete 8-bit, 205 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 205 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports resolutions up to UXGA (1600
×
1200 at 75 Hz).
For ease of design and to minimize cost, the AD9888 is a fully
integrated interface solution for flat panel displays. The AD9888
includes an analog interface with a 205 MHz triple ADC with
internal 1.25 V reference, PLL to generate a pixel clock from
HSYNC and COAST, midscale clamping, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V
power supply, analog input, and HSYNC and COAST signals.
Three-state CMOS outputs may be powered from 2.5 V to 3.3V.
The AD9888’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output frequencies range from
10 MHz to 205 MHz. PLL clock jitter is less than 450 ps p-p
typical at 205 MSPS. When the COAST signal is presented, the
PLL maintains its output frequency in the absence of HSYNC.
A sampling phase adjustment is provided. Data, HSYNC, and
Clock output phase relationships are maintained. The PLL can
be disabled and an external clock input provided as the pixel
clock. The AD9888 also offers full sync processing for compos-
ite sync and Sync-on-Green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9888 is pro-
vided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over the 0
°
C to 70
°
C temperature range.
相關(guān)PDF資料
PDF描述
AD9888KS-100 100/140/170/205 MSPS Analog Flat Panel Interface
AD9888KS-140 TRI N PLUG F 2-13
AD9888KS-170 TRI N RECP M FLG 2-13
AD9888KS-205 TRI N RECP M J/N 2-13
AD9891 CCD Signal Processors with Precision Timing⑩ Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9888/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:100/140/170/205 MSPS Analog Flat Panel Interface
AD9888_11 制造商:AD 制造商全稱:Analog Devices 功能描述:100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface
AD98888KS 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9888KS-100 制造商:Analog Devices 功能描述:ADC Triple 100Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:100 MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk
AD9888KS-140 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:
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