參數(shù)資料
型號(hào)： AD9888
廠商： Analog Devices, Inc.
英文描述： 100/140/170/205 MSPS Analog Flat Panel Interface
中文描述： 100/140/170/205 MSPS的模擬平板顯示接口
文件頁(yè)數(shù)： 25/32頁(yè)
文件大?。?/td> 249K
代理商： AD9888
REV. A
AD9888
–25–
MODE CONTROL 1
15
7
A bit that determines whether all pixels are presented to a
single port (A), or alternating pixels are demultiplexed to
Ports A and B.
Channel Mode
Table XXXIII. Channel Mode Settings
DEMUX
Function
0
1
All data goes to Port A.
Alternate pixels go to Port A and Port B.
When DEMUX = 0, Port B outputs are in a high-
impedance state. The maximum data rate for single-port
mode is 110 MHz. The timing diagrams starting with
Figure 13 show the effects of this option.
The power-up default value is 1.
6
Output Mode
A bit that determines whether all pixels are presented to PortA
and Port B simultaneously on every second DATACK
rising edge, or alternately on Port A and Port B on successive
DATACK rising edges.
15
Table XXXIV. Output Mode Settings
PARALLEL
Function
0
1
Data is interleaved.
Data is simultaneous on every other data
clock.
When in single port mode (DEMUX = 0), this bit is
ignored. The timing diagrams (Figure 17) show the effects
of this option.
The power-up default value is PARALLEL = 1.
5
Output Port Phase
One bit that determines whether even pixels or odd pixels
go to Port A.
15
Table XXXV. Output Port Phase Settings
OUTPHASE
First Pixel after Hsync
0
1
Port A
Port B
In normal operation (OUTPHASE = 0), when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented at Port A. Every
subsequent ODD sample appears at Port A. All EVEN
samples go to Port B.
When OUTPHASE = 1, these ports are reversed and the
first sample goes to Port B.
When DEMUX = 0, this bit is ignored as data always
comes out of only Port A.
4
4:2:2 Output Mode Select
A bit that configures the output data in 4:2:2 mode. This
mode can be used to reduce the number of data lines used
from 24 down to 16 for applications using YUV, YCbCr,
or YPbPr graphics signals. A timing diagram for this mode
15
is shown in Figure 12. Recommended input and output
configurations are shown in Table XXXVII. In 4:2:2
mode, the red and blue channels can be interchanged to
help satisfy board layout or timing requirements, but the
green channel must be configured for Y.
Table XXXVI. 4:2:2 Output Mode Select
Select
Output Mode
0
1
4:4:4
4:2:2
Table XXXVII. 4:2:2 Input/Output Configuration
Channel
Input Connection
Output Format
Red
Green
Blue
V
Y
U
U/V
Y
High Impedance
15
3
A bit that selects either analog inputs from Channel 0 or
the analog inputs from Channel 1.
Input Mux Control
Table XXXVIII. Input Mux Control
Control
Channel Selected
0
1
Channel 0
Channel 1
15
2-1
Two bits that select the analog bandwidth.
Analog Bandwidth Control
Table XXXIX. Analog Bandwidth Control
Bit 2
Bit 1
Analog Bandwidth
1
1
0
0
1
0
1
0
500 MHz
300 MHz
150 MHz
75 MHz
15
0
A bit that determines the source of the pixel clock.
External Clock Select
Table XL. External Clock Select Settings
EXTCLK
Function
0
1
Internally Generated Clock
Externally Provided Clock Signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided HSYNC.
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL Divide Ratio (PLLDIV) is ignored. The
clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
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