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參數(shù)資料
| 型號： | AD9888 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 100/140/170/205 MSPS Analog Flat Panel Interface |
| 中文描述： | 100/140/170/205 MSPS的模擬平板顯示接口 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AD9888 |
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REV. A
AD9888
–11–
C
P
0.0039 F
C
0.039 F
R
3.3k
FILT
PV
D
Figure 6. PLL Loop Filter Detail
Four programmable registers are provided to optimize the per-
formance of the PLL. These registers are:
1. The 12-Bit Divisor Registers. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock fre-
quencies in the range of 10 MHz to 205 MHz. The Divisor
Register controls the exact multiplication factor. This regis-
ter may be set to any value between 221 and 4095. (The
divide ratio that is actually used is the programmed divide
ratio plus one.)
2. The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range register sets this operating range.
Because there are only four possible regions, only the two
least significant bits of the VCO Range register are used. The
frequency ranges for the lowest and highest regions are shown
in Table II.
3. The 3-Bit Charge Pump Current Register. This register allows
the current that drives the low-pass loop filter to be varied.
The possible current values are listed in Table III.
Table II. VCO Frequency Ranges
Pixel Clock Range
(MHz)
K
VCO
Gain
(MHz/V)
PV1
PV0
0
0
1
1
0
1
0
1
10–45
45–90
90–150
150+
22.5
45
90
180
Table III. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current ( A)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
100
150
250
350
500
750
1500
Table IV. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Refresh
Rate (Hz)
Horizontal
Frequency (kHz)
Standard
Resolution
640
×
480
Pixel Rate (MHz)
VCORNGE
Current
VGA
60
72
75
85
31.5
37.7
37.5
43.3
25.175
31.500
31.500
36.000
00
00
00
00
010
100
100
100
SVGA
800
×
600
56
60
72
75
85
35.1
37.9
48.1
46.9
53.7
36.000
40.000
50.000
49.500
56.250
00
00
01
01
01
100
101
011
011
011
XGA
1024
×
768
60
70
75
80
85
48.4
56.5
60.0
64.0
68.3
65.000
75.000
78.750
85.500
94.500
01
01
01
01
10
100
100
101
101
011
SXGA
1280
×
1024
60
75
85
64.0
80.0
91.1
108.000
135.000
157.500
10
10
11
011
100
100
UXGA
1600
×
1200
60
65
70
75
85
75.0
81.3
87.5
93.8
106.3
162.000
175.500
189.000
202.500
229.500
*
11
11
11
11
10
100
100
101
101
110
QXGA
2048
×
1536
2048
×
1536
60
75
260.000
*
315.000
*
11
11
100
100
*
Graphics sampled at 1/2 the incoming pixel rate using Alternate Pixel Sampling mode.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9888/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface |
| AD98888KS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9888KS-100 | 制造商:Analog Devices 功能描述:ADC Triple 100Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:100 MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk |
| AD9888KS-140 | 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述: |
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