參數(shù)資料
型號(hào)： AD9888
廠商： Analog Devices, Inc.
英文描述： 100/140/170/205 MSPS Analog Flat Panel Interface
中文描述： 100/140/170/205 MSPS的模擬平板顯示接口
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 249K
代理商： AD9888
REV. A
AD9888
–19–
Table V. Control Register Map (continued)
Read and
Write or
Read Only
Hex
Address
Default
Value
Bits
Register Name
Function
14H
RO
7:0
Sync Detect
Bit 7—Hsync Detect. It is set to Logic 1 if Hsync is present on the analog
interface, else it is set to Logic 0.
Bit 6—AHS: Active Hsync. This bit indicates which analog Hsync is being
used. (Logic 0 = Hsync input pin, Logic 1 = Hsync from sync-on-green.)
Bit 5—Input Hsync Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Bit 4—Vsync detect. It is set to Logic 1 if Vsync is present on the analog
interface, else it is set to Logic 0.
Bit 3—AVS: Active Vsync. This bit indicates which analog Vsync is being
used. (Logic 0 = Vsync input pin, Logic 1 = Vsync from sync separator.)
Bit 2—Output Vsync Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Bit 1—Sync-on-Green Detect. It is set to Logic 1 if sync is present on the
green video input, else it is set to 0.
Bit 0—Input COAST Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Bit 7—Channel Mode. Determines single-channel or dual-channel output
mode. (Logic 0 = single-channel mode, Logic 1 = dual-channel mode.)
Bit 6—Output Mode. Determine interleaved or parallel output mode.
(Logic 0 = interleaved mode, Logic 1 = parallel mode.)
Bit 5—A/B Invert. Determines which port outputs the first data byte after
Hsync. (Logic 0 = A port, Logic 1 = B port.)
Bit 4—4:2:2 Output Formatting Mode.
Bit 3—Input Mux Control.
Bits [2:1]—Input Bandwidth.
Bit 0—External Clock. Shuts down PLL and allows external clock to drive the
part. (Logic 0 = use internal PLL, Logic 1 = bypassing of the internal PLL.)
Must be set to 11111110 for proper operation.
Must be set to default for proper operation.
15H
R/
W
7:0
1
*******
*
1
******
**
0
*****
***
0
****
****
0
***
*****
11
*
*******
0
16H
17H
18H
19H
R/
W
R/
W
RO
RO
7:0
7:3
7:0
7:0
11111111 Test Register
00000000 Test Register
Test Register
Test Register
NOTE
1. The AD9888 only updates the PLL divide ratio when the LSBs are written to (Register 02h).
相關(guān)PDF資料
PDF描述
AD9888KS-100 100/140/170/205 MSPS Analog Flat Panel Interface
AD9888KS-140 TRI N PLUG F 2-13
AD9888KS-170 TRI N RECP M FLG 2-13
AD9888KS-205 TRI N RECP M J/N 2-13
AD9891 CCD Signal Processors with Precision Timing⑩ Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9888/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:100/140/170/205 MSPS Analog Flat Panel Interface
AD9888_11 制造商:AD 制造商全稱:Analog Devices 功能描述:100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface
AD98888KS 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9888KS-100 制造商:Analog Devices 功能描述:ADC Triple 100Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:100 MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk
AD9888KS-140 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述:
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