- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD9888 (Analog Devices, Inc.) 100/140/170/205 MSPS Analog Flat Panel Interface PDF資料下載
參數(shù)資料
| 型號： | AD9888 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 100/140/170/205 MSPS Analog Flat Panel Interface |
| 中文描述： | 100/140/170/205 MSPS的模擬平板顯示接口 |
| 文件頁數(shù)： | 23/32頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AD9888 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
REV. A
AD9888
–23–
0F
3
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
COAST Input Polarity
Table XX. COAST Input Polarity Settings
CSTPOL
Function
0
1
Active LOW
Active HIGH
Active LOW means that the clock generator will ignore
Hsync inputs when COAST is LOW, and continue
operating at the same nominal frequency until COAST
goes HIGH.
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue
operating at the same nominal frequency until COAST
goes LOW.
This function needs to be used along with the COAST
polarity override bit (Bit 4).
The power-up default value is CSTPOL = 1.
2
Seek Mode Override
This bit is used to either allow or disallow the low-power
mode. The low-power mode (seek mode) occurs when
there are no signals on any of the Sync inputs.
0F
Table XXI. Seek Mode Override Settings
Select
Result
1
0
Allow Seek Mode
Disallow Seek Mode
The default for this register is 1.
1
PWRDN
This bit is used to put the chip in power-down mode. In this
mode the chip’s power dissipation is reduced to a fraction
of the typical power (see the Electrical Characteristics
table for exact power dissipation). When in power-down,
the HSOUT, VSOUT, DATACK,
DATACK
, and all 48
of the data outputs are put into a high impedance state.
(Note: the SOGOUT output is not put into high imped-
ance.) Circuit blocks that continue to be active during
power-down include the voltage references, sync process-
ing, sync detection, and the serial register. These blocks
facilitate a fast start-up from power-down.
0F
Table XXII. Power-Down Settings
Select
Result
0
1
Power-Down
Normal Operation
The default for this register is 1.
7-3
Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the Sync-
on-Green slicer to be adjusted. This register adjusts it in
steps of 10 mV, with the minimum setting equaling 10mV
and the maximum setting equaling 330 mV.
10
The default setting is 15 and corresponds to a threshold
value of 0.16 V.
2
Red Clamp Select
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 9.
10
Table XXIII. Red Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 9)
The default setting for this register is 0.
1
Blue Clamp Select
A bit that determines whether the blue channel is clamped
to ground or to midscale. Clamping to midscale actually
clamps to Pin 24.
10
Table XXIV. Blue Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 24)
The default setting for this register is 0.
7:0
Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many internal 5 MHz clock periods
the sync separator must count to before toggling high or
low. It works like a low-pass filter to ignore Hsync pulses
in order to extract the Vsync signal. This register should
be set to some number greater than the maximum Hsync
pulsewidth. Note: the sync separator threshold uses an
internal dedicated clock with a frequency of approxi-
mately 5 MHz.
The default for this register is 32.
7-0
Pre-COAST
This register allows the COAST signal to be applied prior
to the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
7-0
Post-COAST
This register allows the COAST signal to be applied
following to the Vsync signal. This is necessary in cases
where post-equalization pulses are present. The step size
for this control is one Hsync period.
The default is 0.
11
12
13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9888KS-100 | 100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888KS-140 | TRI N PLUG F 2-13 |
| AD9888KS-170 | TRI N RECP M FLG 2-13 |
| AD9888KS-205 | TRI N RECP M J/N 2-13 |
| AD9891 | CCD Signal Processors with Precision Timing⑩ Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9888/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface |
| AD98888KS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9888KS-100 | 制造商:Analog Devices 功能描述:ADC Triple 100Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:100 MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk |
| AD9888KS-140 | 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。