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參數(shù)資料
| 型號： | AD9888 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 100/140/170/205 MSPS Analog Flat Panel Interface |
| 中文描述： | 100/140/170/205 MSPS的模擬平板顯示接口 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AD9888 |
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REV. A
AD9888
–7–
PIN FUNCTION DESCRIPTIONS (continued)
Pin
Description
CKINV
Sampling Clock Inversion (Optional)
This pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180
°
. This is
in support of Alternate Pixel Sampling mode, wherein higher-frequency input signals (up to 410 Mpps) may be captured by
first sampling the odd pixels, then capturing the even pixels on the subsequent frame.
This pin should be exercised only during blanking intervals (typically vertical blanking) as it may produce several
samples of corrupted data during the phase shift.
CKINV should be grounded when not used.
Outputs
D
R
A
7-0
D
R
B
7-0
D
G
A
7-0
D
G
B
7-0
D
B
A
7-0
D
B
B
7-0
Data Output, Red Channel, Port A
Data Output, Red Channel, Port B
Data Output, Green Channel, Port A
Data Output, Green Channel, Port B
Data Output, Blue Channel, Port A
Data Output, Blue Channel, Port B
These are the main data outputs. Bit 7 is the MSB.
Each channel has two ports. When the part is operated in single-channel mode (Channel Mode bit (15H, Bit 7) = 0), all
data are presented to Port A, and Port B is placed in a high-impedance state.
Programming the Channel Mode bit to 1 establishes dual-channel mode, wherein alternate pixels are presented to Port A
and
Port B of each channel. These will appear simultaneously; two pixels are presented at the time of every second input
pixel, when the Output Mode bit (15H, Bit 6) is set to 1 (parallel mode). When the Output Mode bit is set
to 0, pixel
data appear alternately on the two ports, one new sample with each incoming pixel (interleaved mode).
In dual-channel mode, the first pixel after HSYNC is routed to Port A. The second pixel goes to Port B, the third to A,
etc. This can be reversed by setting the A/B Invert bit to 1 (15H, Bit 5).
The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the PHASE
regis-
ter, the output timing is shifted as well. The DATACK,
DATACK
and HSOUT outputs are also moved, so the
timing relationship among the signals is maintained.
Data Output Clock
Data Output Clock Complement
Differential data clock output signals to be used to strobe the output data and HSOUT into external logic.
They are produced by the internal clock generator and are synchronous with the internal pixel sampling clock.
When the AD9888 is operated in single-channel mode, the output frequency is equal to the pixel sampling frequency.
When operating in dual-channel mode, the clock frequency is one-half the pixel frequency, as is the output data frequency.
When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The Data,
DATACK,
DATACK
and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.
Either or both signals may be used, depending on the timing mode and interface design employed.
Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be
programmed via serial bus registers.
By maintaining alignment with DATACK,
DATACK
, and Data, data timing with respect to horizontal sync can always
be determined.
Sync-On-Green Slicer Output
This pin can be programmed to output either the output from the Sync-On-Green slicer comparator or an unproc-
essed but delayed version of the Hsync input. See the Sync Processing Block Diagram (Figure 25) to view how this pin is
connected. (Note: Besides slicing off SOG, the output from this pin gets no other additional processing on the AD9888.
Vsync separation is performed via the sync separator.)
Internal Reference BYPASS
Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1
μ
F capacitor. The abso-
lute accuracy of this reference is
±
4%, and the temperature coefficient is
±
50 ppm, which is adequate for most AD9888
applications. If higher accuracy is required, an external reference may be employed instead.
RED Channel Midscale Voltage BYPASS
BLUE Channel Midscale Voltage BYPASS
Bypasses for the internal midscale voltage references. They should each be connected to ground through 0.1
μ
F
capacitors. The exact voltage varies with the gain setting of the BLUE channel.
DATACK
DATACK
HSOUT
SOGOUT
REF BYPASS
RMIDSCV
BMIDSCV
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9888KS-100 | 100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888KS-140 | TRI N PLUG F 2-13 |
| AD9888KS-170 | TRI N RECP M FLG 2-13 |
| AD9888KS-205 | TRI N RECP M J/N 2-13 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9888/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface |
| AD98888KS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9888KS-100 | 制造商:Analog Devices 功能描述:ADC Triple 100Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:100 MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk |
| AD9888KS-140 | 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述: |
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