參數(shù)資料
型號(hào)： AD9865CHIPS
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Broadband Modem Mixed-Signal Front End
中文描述： SPECIALTY TELECOM CIRCUIT, UUC
封裝： DIE
文件頁(yè)數(shù)： 26/48頁(yè)
文件大?。?/td> 1672K
代理商： AD9865CHIPS
AD9865
Rev. A | Page 26 of 48
4
6-BIT DIGITAL WORD-DECIMAL EQUIVALENT
G
0
48
24
60
66
–12
–6
0
6
12
18
24
30
36
42
54
42
48
30
36
6
12
18
Figure 56. Digital Gain Mapping of RxPGA
Table 15. SPI Registers RxPGA Control
Address
(Hex)
Bit
Description
0x09
(6)
Enable RxPGA update via SPI
(5:0)
RxPGA gain code
0x0B
(6)
Select TxPGA via PGA[5:0]
(5)
Select RxPGA via PGA[5:0]
(3)
Enable software GAIN strobe – Full-duplex
(2)
Enable RxPGA update via Tx[5:0] – Full-duplex
(1)
3-bit RxPGA gain mapping – Half-duplex
The RxPGA gain register can be updated via the Tx[5:0] port,
the PGA[5:0] port, or the SPI port. The first two methods allow
fast updates of the RxPGA gain register and should be
considered for digital AGC functions requiring a fast closed-
loop response. The SPI port allows direct update and readback
of the RxPGA gain register via Register 0x09 with an update
rate limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6
of Register 0x09 must be set for a read or write operation.
Updating the RxPGA via the Tx[5:0] port is an option only in
full-duplex mode
1
. In this case, a high level on the GAIN pin,
2
with TXSYNC low, programs the PGA setting on either the
rising edge or falling edge of RXCLK, as shown in Figure 57.
The GAIN pin must be held high, TXSYNC must be held low,
and GAIN data must be stable for one or more clock cycles to
update the RxPGA gain setting.
A low level on the GAIN pin enables data to be fed to the digital
interpolation filter. This interface should be considered when
upgrading existing designs from the AD9875/AD9876 MxFE
products or half-duplex applications trying to minimize an
ASIC’s pin count.
t
SU
RXCLK
Tx SYNC
Tx [5:0]
t
HD
GAIN
GAIN
4
Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode
Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an
option for both the half-duplex
3
and full-duplex interface. The
PGA port consists of an input buffer that passes the 6-bit data
appearing at its input directly to the RxPGA (or TxPGA) gain
register with no gating signal required. Bit 5 or Bit 6 of
Register 0x0B is used to select whether the data updates the
RxPGA or TxPGA gain register. In applications that switch
between RxPGA and TxPGA gain control via PGA[5:0], be
careful that the RxPGA (or TxPGA) is not inadvertently loaded
with the wrong data during a transition. In the case of an
RxPGA to TxPGA transition, first deselect the RxPGA gain
register, update the PGA[5:0] port with the desired TxPGA gain
setting, and then select the TxPGA gain register.
The RxPGA also offers an alternative 3-bit word gain mapping
option
4
that provides a 12 dB to +36 dB span in 8 dB increments
as shown in Table 16. The 3-bit word is directed to PGA[5:3]
with PGA[5] being the MSB. This feature is backward-compatible
with the AD9975 MxFE and allows direct interfacing to the
CX11647 or INT5130 HomePlug 1.0 PHYs.
Table 16. PGA Timing for AD9975 Backward-Compatible
Mode
Digital Gain Setting
PGA[5:3]
Decimal
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Gain (dB)
12
12
4
4
12
20
28
36
1
Default setting for full-duplex mode (MODE = 1).
2
The GAIN strobe can also be set in software via Reg. 0x0B, Bit 3 for
continuous updating. This eliminates the requirement for external GAIN
signal, reducing the ASIC pin count by 1.
3
Default setting for half-duplex mode (MODE = 0).
4
Default setting for MODE = 0 and CONFIG =1.
相關(guān)PDF資料
PDF描述
AD9887 Dual Interface for Flat Panel Displays
AD9888 100/140/170/205 MSPS Analog Flat Panel Interface
AD9888KS-100 100/140/170/205 MSPS Analog Flat Panel Interface
AD9888KS-140 TRI N PLUG F 2-13
AD9888KS-170 TRI N RECP M FLG 2-13
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9865-EB 制造商:Analog Devices 功能描述:MODEM, BROADBAND MODEM MIXED SGNL FRONT END - Bulk
AD9866 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End
AD9866BCP 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9866
AD9866BCPRL 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R
AD9866BCPZ 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*