參數(shù)資料
型號： AD9865CHIPS
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Broadband Modem Mixed-Signal Front End
中文描述： SPECIALTY TELECOM CIRCUIT, UUC
封裝： DIE
文件頁數(shù)： 4/48頁
文件大?。?/td> 1672K
代理商： AD9865CHIPS
AD9865
Parameter
Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation)
Latency (Relative to 1/ F
DAC
)
0.2 dB Bandwidth
3 dB Bandwidth
Stop Band Rejection (0.289 f
OSCIN
to 0.711 f
OSCIN
)
PLL CLK MULTIPLIER
OSCIN Frequency Range
Internal VCO Frequency Range
Duty Cycle
OSCIN Impedance
CLKOUT1 Jitter
5
CLKOUT2 Jitter
6
CLKOUT1 and CLKOUT2 Duty Cycle
7
Rev. A | Page 4 of 48
Temp
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
Full
Test Level
V
V
V
V
IV
IV
II
V
III
III
III
Min
5
20
40
45
Typ
96
0.1095
0.1202
50
100//3
12
6
Max
80
200
60
55
Unit
Cycles
f
OUT
/f
DAC
f
OUT
/f
DAC
dB
MHz
MHz
%
Μ/pF
ps rms
ps rms
%
1
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).
2
TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 , F
OUT
= 5 MHz, 4x interpolation.
3
IOUN full-scale current = 80 mA, f
OSCIN
= 80 MHz, f
DAC
=160 MHz, 2x interpolation.
4
Use external amplifier to drive additional load.
5
Internal VCO operates at 200 MHz , set to divide-by
-
1.
6
Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN.
7
CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
Rx PATH SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default power bias
settings, unless otherwise noted.
Table 2.
Parameter
Rx INPUT CHARACTERISTICS
Input Voltage Span (RxPGA Gain = 10 dB)
Input Voltage Span (RxPGA Gain = +48 dB)
Input Common-Mode Voltage
Differential Input Impedance
Temp
Full
Full
25°C
25°C
Test Level
III
III
III
III
Min
Typ
6.33
8
1.3
400
4.0
53
3.0
2.4
12
48
1
Monotonic
0.5
20
±1
20
100
10
Max
Unit
V p-p
mV p-p
V
pF
MHz
nV/rtHz
nV/rtHz
dB
dB
dB
dB
dB
MHz
dB
dB
ns
ns
Bits
MSPS
Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB)
Input Voltage Noise Density (RxPGA Gain = 36 dB, f
3 dBF
= 26 MHz)
Input Voltage Noise Density (RxPGA Gain = 48 dB, f
3 dBF
= 26 MHz)
RxPGA CHARACTERISTICS
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
Gain Range Error
RxLPF CHARACTERISTICS
Cutoff Frequency (f
3 dBF
) Range
Attenuation at 55.2 MHz with f
3 dBF
= 21 MHz
Pass-Band Ripple
Settling Time to 5 dB RxPGA Gain Step @ f
ADC
= 50 MSPS
Settling Time to 60 dB RxPGA Gain Step @ f
ADC
= 50 MSPS
ADC DC CHARACTERISTICS
Resolution
Conversion Rate
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
NA
Full
III
III
III
III
III
III
III
III
III
III
III
III
III
NA
II
15
5
35
80
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