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參數(shù)資料
| 型號(hào)： | AD9865CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | AD9865CHIPS |
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AD9865
Rev. A | Page 21 of 48
Power-Up Default Value
MODE = 0 (Half-Duplex)
CONFIG = 0
MODE = 1 (Full-Duplex)
CONFIG = 0
Address
(Hex)
1
0x13
Bit
Break-
down
(7:5)
(4:3)
(2:0)
Description
CPGA Bias Adjust
SPGA Bias Adjust
ADC Bias Adjust
Width
3
2
4
CONFIG = 1
CONFIG = 1
Comments
Current bias setting for Rx
path’s functional blocks.
Refer to page 41.
0x00
0x00
0x00
0x00
1
Bits that are undefined should always be assigned a 0.
REGISTER MAP DESCRIPTION
The AD9865 contains a set of programmable registers described
in Table 10 that are used to optimize its numerous features,
interface options, and performance parameters from its default
register settings. Registers pertaining to similar functions have
been grouped together and assigned adjacent addresses to
minimize the update time when using the multibyte serial port
interface (SPI) read/write feature. Bits that are undefined within
a register should be assigned a 0 when writing to that register.
The default
register settings were intended to allow some
applications to operate without the use of an SPI. The AD9865
can be configured to support a half- or full-duplex digital
interface via the MODE pin, with each interface having two
possible default
register settings determined by the setting of
the CONFIG pin.
For instance, applications that need to use only the Tx or Rx
path functionality of the AD9865 can configure it for a half-
duplex interface (MODE = 0), and use the TXEN pin to select
between the Tx or Rx signal path with the unused path
remaining in a reduced power state. The CONFIG pin can be
used to select the default
interpolation ratio of the Tx path and
RxPGA gain mapping.
SERIAL PORT INTERFACE (SPI)
The serial port of the AD9865 has 3- or 4-wire SPI capability
allowing read/write access to all registers that configure the
device’s internal parameters. Registers pertaining to the SPI are
listed in Table 11. The default 3-wire serial communication port
consists of a clock (SCLK), serial port enable (SEN), and a bi-
directional data (SDIO) signal. SEN is an active low control
gating read and write cycle. When SEN is high, SDO and SDIO
are three-stated. The inputs to SCLK, SEN, and SDIO contain a
Schmitt trigger with a nominal hysteresis of 0.4 V centered
about VDDH/2. The SDO pin remains three-stated in a 3-wire
SPI interface.
Table 11. SPI Registers Pertaining to SPI Options
Address (Hex)
0x00
Bit
(7)
(6)
Description
Enable 4-wire SPI
Enable SPI LSB first
A 4-wire SPI can be enabled by setting the 4-wire SPI bit high
,
causing the output data to appear on the SDO pin instead of on
the SDIO pin. The SDIO pin serves as an input-only throughout
the read operation. Note that the SDO pin is active only during
the transmission of data and remains three-stated at any other
time.
An 8-bit instruction header must accompany each read and
write operation. The instruction header is shown in Table 12.
The MSB is an R/W indicator bit with logic high indicating a
read operation. The next two bits, N1 and N0, specify the
number of bytes (one to four bytes) to be transferred during the
data transfer cycle. The remaining five bits specify the address
bits to be accessed during the data transfer portion. The data
bits immediately follow the instruction header for both read
and write operations.
Table 12. Instruction Header Information
MSB
17
16
15
R/W
N1
N0
14
A4
13
A3
12
A2
LSB
11
A1
10
A0
The AD9865 serial port can support both MSB (most
significant bit) first and LSB (least significant bit) first data
formats. Figure 45 illustrates how the serial port words are built
for the MSB first and LSB first modes. The bit order is con-
trolled by the SPI LSB first bit (Register 0, Bit 6). The default
value is 0, MSB first. Multibyte data transfers in MSB format
can be completed by writing an instruction byte that includes
the register address of the last address to be accessed. The
AD9865 automatically decrements the address for each succes-
sive byte required for the multibyte communication cycle.
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