參數(shù)資料
型號(hào)： AD9865CHIPS
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Broadband Modem Mixed-Signal Front End
中文描述： SPECIALTY TELECOM CIRCUIT, UUC
封裝： DIE
文件頁(yè)數(shù)： 35/48頁(yè)
文件大?。?/td> 1672K
代理商： AD9865CHIPS
AD9865
Rev. A | Page 35 of 48
4
TARGET-DECIMAL EQUIVALENT
F
48
128
224
192
96
112
176
80
64
35
15
17
19
21
23
25
27
29
31
33
144
160
208
50 MSPS CALCULATED
80 MSPS CALCULATED
50 MSPS MEASURED
80 MSPS MEASURED
Figure 73. Measured and Calculated f
3 dB
vs. Target Value
for f
ADC
= 50 MSPS and 80 MSPS
The following scaling factor can be applied to the previous
formula to compensate for the RxPGA gain setting on f
3 dB
:
Scale Factor
= 1 (
RxPGA in dB
)/382
(9)
This scaling factor reduces the calculated f
3 dB
as the RxPGA is
increased. Applications that need to maintain a minimum cut-
off frequency, f
3 dB_MIN
, for all RxPGA gain settings should first
determine the scaling factor for the highest RxPGA gain setting
to be used. Next, the f
3 dB_MIN
should be divided by this scale
factor to normalize to the 0 dB RxPGA gain setting (f
3 dB_0 dB
).
Equation 8 can then be used to calculate the target value.
The LPF frequency response shows a slight sensitivity to
temperature, as shown in Figure 74. Applications sensitive to
temperature drift can recalibrate the LPF by rewriting the target
value to Register 0x08.
4
TARGET-DECIMAL EQUIVALENT
F
96
128
240
192
176
112
35
15
20
25
30
144
160
208
F
OUT
ACTUAL 80MHz AND –40
°
C
224
F
OUT
ACTUAL 80MHz AND +25
°
C
F
OUT
ACTUAL 80MHz AND +85
°
C
Figure 74. Temperature Drift of f
3 dB
for f
ADC
= 80 MSPS and RxPGA = 0 dB
ANALOG-TO-DIGITAL CONVERTER (ADC)
The AD9865 features a 10-bit analog-to-digital converter
(ADC) capable of up to 80 MSPS. Referring to Figure 68, the
ADC is driven by the SPGA stage, which performs both the
sample-and-hold and the fine gain adjust functions. A buffer
amplifier (not shown) isolates the last CPGA gain stage from
the dynamic load presented by the SPGA stage. The full-scale
input span of the ADC is 2 V p-p, and depending on the PGA
gain setting, the full-scale input span into the SPGA is
adjustable from 1 V to 2 V in 1 dB increments.
A pipelined multistage ADC architecture is used to achieve high
sample rates while consuming low power. The ADC distributes
the conversion over several smaller A/D subblocks, refining the
conversion with progressively higher accuracy as it passes the
results from stage to stage on each clock edge. The ADC typi-
cally performs best when driven internally by a 50% duty cycle
clock. This is especially the case when operating the ADC at
high sample rate (55 MSPS to 80 MSPS) and/or lower internal
bias levels, which adversely affect interstage settling time
requirements.
The ADC sampling clock path also includes a duty cycle
restorer circuit, which ensures that the ADC gets a near 50%
duty cycle clock even when presented with a clock source with
poor symmetry (35/65). This circuit should be enabled if the
ADC sampling clock is a buffered version of the reference signal
appearing at OSCIN (see the Clock Synthesizer section), and if
this reference signal is derived from an oscillator or crystal
whose specified symmetry cannot be guaranteed to be within
45/55 (or 55/45). This circuit can remain disabled if the ADC
sampling clock is derived from a divided down version of the
clock synthesizer’s VCO, because this clock is near 50%.
The ADC’s power consumption can be reduced by 25 mA, with
minimal effect on its performance, by setting Bit 4 of Register
0x07. Alternative power bias settings are also available via
Register 0x13, as discussed in the Power Control and
Dissipation section. Lastly, the ADC can be completely powered
down for half-duplex operation, further reducing the AD9865’s
peak power consumption.
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