參數(shù)資料
型號(hào): 28F640J5
英文描述: Dual-Slot, PCMCIA Analog Power Controller
中文描述: 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù),32和64兆比特
文件頁(yè)數(shù): 51/53頁(yè)
文件大小: 306K
代理商: 28F640J5
E
6.7
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
51
PRELIMINARY
Block Erase, Program, and Lock-Bit Configuration Performance
(3,4)
#
Sym
Parameter
Notes
2,5
Min
TBD
Typ
(1)
6.3
Max
TBD
Unit
μs
W16 t
WHQV1
t
EHQV1
W16 t
WHQV2
t
EHQV2
W16 t
WHQV3
t
EHQV3
Write Buffer Byte Program Time
Write Buffer Word Program Time
2,5
TBD
12.6
TBD
μs
Byte Program Time (Using
Word/Byte Program Command)
Block Program Time (Using Write
to Buffer Command)
Block Erase Time
2
TBD
180
TBD
μs
2
TBD
0.8
TBD
sec
W16 t
WHQV4
t
EHQV4
W16 t
WHQV5
t
EHQV5
W16 t
WHQV6
t
EHQV6
W16 t
WHRH
t
EHRH
NOTES:
1.
Typical values measured at T
= +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2.
Excludes system-level overhead.
3.
These performance numbers are valid for all speed versions.
4.
Sampled but not 100% tested.
5.
These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
2
TBD
0.7
TBD
sec
Set Lock-Bit Time
2
TBD
32
TBD
μs
Clear Block Lock-Bits Time
2
TBD
0.3
TBD
sec
Erase Suspend Latency Time to
Read
26
TBD
μs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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