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參數(shù)資料
| 型號： | 28F640J5 |
| 英文描述： | Dual-Slot, PCMCIA Analog Power Controller |
| 中文描述： | 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù)，32和64兆比特 |
| 文件頁數(shù)： | 31/53頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 28F640J5 |
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E
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
31
PRELIMINARY
Table 15. Configuration Coding Definitions
Reserved
Pulse On
Program
Complete
(1)
Pulse On
Erase
Complete
(1)
bits 7
–2
bit 1
bit 0
DQ7
–DQ2= Reserved
DQ1–DQ0= STS Pin Configuration Codes
00 =
default, level mode RY/BY#
(device ready) indication
01 =
pulse on Erase complete
10 =
pulse on Program complete
11 =
pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high
when the operation indicated by the given
configuration is completed.
Configuration Command Sequences for STS pin
configuration (masking bits DQ7–DQ2 to 00h) are
as follows:
Default RY/BY# level mode:
ER INT (Erase Interrupt):
Pulse-on-Erase Complete
PR INT (Program Interrupt):
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt):
Pulse-on-Erase or Program Complete
B8h, 00h
B8h, 01h
B8h, 02h
B8h, 03h
DQ7–DQ2 are reserved for future use.
default (DQ1–DQ0 = 00)
— used to control HOLD to a memory controller to
prevent accessing a flash memory subsystem while
any flash device's WSM is busy.
RY/BY#, level mode
configuration 01
— used to generate a system interrupt pulse when
any flash device in an array has completed a Block
Erase or sequence of Queued Block Erases. Helpful
for reformatting blocks after file system free space
reclamation or “cleanup”
ER INT, pulse mode
configuration 10
— used to generate a system interrupt pulse when
any flash device in an array has complete a Program
operation. Provides highest performance for servicing
continuous buffer write operations.
PR INT, pulse mode
configuration 11
— used to generate system interrupts to trigger
servicing of flash arrays when either erase or
program operations are completed when a common
interrupt service routine is desired.
ER/PR INT, pulse mode
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
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