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參數(shù)資料
| 型號： | 28F640J5 |
| 英文描述： | Dual-Slot, PCMCIA Analog Power Controller |
| 中文描述： | 28F640J5 -英特爾StrataFlash內存技術，32和64兆比特 |
| 文件頁數(shù)： | 25/53頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 28F640J5 |
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E
4.2.7
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
25
PRELIMINARY
PRIMARY-VENDOR SPECIFIC EXTENDED QUERY TABLE
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table
specifies this and other similar information.
Table 12. Primary Vendor-Specific Extended Query
Offset
(1)
Length
(bytes)
Description
Intel
StrataFlash
Memory
(P)h
03h
Primary extended Query table unique ASCII string
“PRI”
31:
32:
33:
0050h
0052h
0049h
(P +3)h
01h
Major version number, ASCII
34:
0031
(P +4)h
01h
Minor version number, ASCII
35:
0031
(P +5)h
04h
Optional Feature and Command Support
bit 0
bit 1
bit 2
bit 3
bit 4
Chip Erase Supported
Suspend Erase Supported
Suspend Program Supported
Lock/Unlock Supported
Queued Erase Supported
(1=yes,
0=no
)
(
1=yes
, 0=no)
(1=yes,
0=no
)
(
1=yes
, 0=no)
(1=yes,
0=no
)
bits 5
–31
Reserved for future use; undefined bits
are “0”
36:
37:
38:
39:
000Ah
0000h
0000h
0000h
(P +9)h
01h
Supported functions after Suspend
Read Array, Status, and Query are always supported
during suspended Erase. This field defines other
operations supported.
bit 0
(
1=yes
, 0=no)
Program supported after Erase Suspend
bits 1–7
Reserved for future use; undefined bits
are “0”
3A:
0001h
(P +A)h
02h
Block Status Register Mask
Defines which bits in the Block Status Register section of
Query are implemented.
bit 0
Block Status Register Lock Bit [BSR.0] active
(
1=yes
, 0=no)
Block Status Register Valid Bit [BSR.1] active
(1=yes,
0=no
)
bit 1
bits 2–15
Reserved for future use; undefined bits
are “0”
3B:
3C:
0001h
0000h
NOTE:
1. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software
should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.
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相關代理商/技術參數(shù) |
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|---|---|
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