參數(shù)資料
型號(hào): 28F640J5
英文描述: Dual-Slot, PCMCIA Analog Power Controller
中文描述: 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù),32和64兆比特
文件頁(yè)數(shù): 33/53頁(yè)
文件大?。?/td> 306K
代理商: 28F640J5
E
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
33
PRELIMINARY
Table 17. eXtended Status Register Definitions
WBS
Reserved
bit 7
bits 6
–0
High Z
When
Busy
Status Register Bits
NOTES:
No
Yes
XSR.7 = WRITE BUFFER STATUS
1 = Write buffer available
0 = Write buffer not available
XSR.6
–XSR.0
ENHANCEMENTS
=
RESERVED FOR FUTURE
After a Buffer-Write command, XSR.7 = 1
indicates that a Write Buffer is available.
SR.6–SR.0 are reserved for future use and
should be masked when polling the status
register.
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相關(guān)代理商/技術(shù)參數(shù)
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