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XRT79L71
PRELIMINARY
387
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
The Receive E3 Framer block will clear the "FERF/RDI Defect Condition" whenever it receives a "User-
Selectable" number of E3 frames, in which the "A" bit-field is set to "0".
Setting the FERF/RDI Defect Clearance Criteria
The user can specify the "FERF/RDI Defect Clearance" Criteria by writing the appropriate value into Bit 4
(RxFERF Algo), as depicted below.
If this bit-field is set to "0", then the Receive E3 Framer block will clear the "FERF/RDI" defect condition
anytime it receives at least three (3) consecutive E3 frames, in which the "A" bit-field has been set to "0".
Conversely, if this bit-field is set to "1", then the Receive E3 Framer block will clear the "FERF/RDI" defect
condition anytime it receives at least five (5) consecutive E3 frames, in which the "A" bit-field has been set to
"0".
Whenever the Receive E3 Framer block clears the FERF/RDI defect condition, it will do so, by doing all of the
following.
Setting Bit 0 (FERF/RDI Defect Condition Declared) within the "Receive E3 Configuration and Status # 2" to
"0" as depicted below.
The Receive E3 Framer block will also generate the "Change in FERF/RDI Defect Condition" Interrupt, by
asserting the Interrupt Output pin (e.g., by pulling it "LOW") and setting Bit 3 (Change of FERF/RDI Defect
Condition Interrupt Status), within the "Receive E3 Interrupt Status Register # 2" to "1" as depicted below.
Receive E3 Configuration and Status Register # 1 - G.751 (Address = 0x1110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
RxFERF
Algo
Unused
RxBIP-4
Enable
R/O
R/W
R/O
R/W
0
X
0
Receive E3 Configuration and Status Register # 2 - G.751 (Address = 0x1111)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
LOF
Algo
LOF
Defect
Condition
Declared
OOF
Defect
Condition
Declared
LOS
Defect
Condition
Declared
AIS Defect
Condition
Declared
Unused
FERF/RDI
Defect
Condition
Declared
R/W
R/O
X
0