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XRT79L71
PRELIMINARY
383
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
5.3.2.4.1
Declaring the AIS Defect Condition
If the XRT79L71 has been configured to operate in the "E3, ITU-T G.751 Framing format, then the Receive E3
Framer block will declare the AIS defect condition anytime it receives an E3 data-stream that contains 7 or less
"0s" within two consecutive E3 frame periods.
If the Receive E3 Framer block declares the AIS defect condition, then it will do all of the following.
It will set Bit 3 (AIS Defect Condition Declared)
The Receive E3 Framer block will also generate the "Change in AIS Defect Condition" Interrupt request by
asserting the Interrupt Output pin (e.g., by pulling it "LOW") and setting Bit 0 (Change in AIS Defect
Condition Interrupt Status), within the Receive E3 Interrupt Status Register # 1" to "1" as depicted below.
5.3.2.4.2
Clearing the AIS Defect Condition
The Receive E3 Framer block will clear the "AIS Defect" condition whenever it receives two consecutive E3
frames that contain 8 or more "0s", within the incoming E3 data-stream. The Receive E3 Framer block will
indicate that it is clearing the AIS defect by:
It will set Bit 3 (AIS Defect Condition Declared), within the Receive E3 Configuration and Status Register # 2"
to "0", as depicted below.
Receive E3 Configuration and Status Register # 2 - G.751 (Address = 0x1111)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
LOF
Algo
LOF
Defect
Condition
Declared
OOF
Defect
Condition
Declared
LOS
Defect
Condition
Declared
AIS Defect
Condition
Declared
Unused
FERF/RDI
Defect
Condition
Declared
R/W
R/O
X
0
1
0
Receive E3 Interrupt Status Register # 1 - G.751 (Address = 0x1114)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
COFA
Interrupt
Status
Change in
OOF Defect
Condition
Interrupt
Status
Change in
LOF Defect
Condition
Interrupt
Status
Change in
LOS Defect
Condition
Interrupt
Status
Change in
AIS Defect
Condition
Interrupt
Status
R/O
RUR
0
1