參數(shù)資料
型號： XC2S150E-6FT256I
廠商： Xilinx Inc
文件頁數(shù)： 59/108頁
文件大?。?/td> 0K
描述： SPARTAN FPGA 150000 GATE 1.8V
產品變化通告： FPGA Family Discontinuation 18/Apr/2011
標準包裝： 90
系列： Spartan®-IIE
LAB/CLB數(shù)： 864
邏輯元件/單元數(shù)： 3888
RAM 位總計： 49152
輸入/輸出數(shù)： 182
門數(shù)： 150000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應商設備封裝： 256-FTBGA
其它名稱： Q1280323
54
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
D0/DIN, D1, D2, D3,
D4, D5, D6, D7
No
Input or Output
In Slave Parallel mode, D0-D7 are configuration data input pins.
During readback, D0-D7 are output pins. These pins become
user I/Os after configuration unless the Slave Parallel port is
retained.
In serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
WRITE
No
Input
In Slave Parallel mode, the active-low Write Enable signal. This
pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
CS
No
Input
In Slave Parallel mode, the active-low Chip Select signal. This pin
becomes a user I/O after configuration unless the Slave Parallel
port is retained.
TDI, TDO, TMS, TCK
Yes
Mixed
Boundary Scan Test Access Port pins (IEEE 1149.1).
VCCINT
Yes
Input
1.8V power supply pins for the internal core logic.
VCCO
Yes
Input
Power supply pins for output drivers (1.5V, 1.8V, 2.5V, or 3.3V
subject to banking rules in the Functional Description module.
VREF
No
Input
Input threshold reference voltage pins. Become user I/Os when
an external threshold voltage is not needed (subject to banking
rules in the Functional Description module.
GND
Yes
Input
Ground. All must be connected.
IRDY, TRDY
No
See PCI core
documentation
These signals can only be accessed when using Xilinx PCI cores.
If the cores are not used, these pins are available as user I/Os.
L#[P/N]
(e.g., L0P)
No
Bidirectional
Differential I/O with synchronous output. P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
L#[P/N]_Y
(e.g., L0P_Y)
No
Bidirectional
Differential I/O with asynchronous or synchronous output
(asynchronous output not compatible for all densities in a
package). P = positive, N = negative. The number (#) is used to
associate the two pins of a differential pair. Becomes a general
user I/O when not needed for differential signals.
L#[P/N]_YY
(e.g., L0P_YY)
No
Bidirectional
Differential I/O with asynchronous or synchronous output
(compatible for all densities in a package). P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
I/O
No
Bidirectional
These pins can be configured to be input and/or output after
configuration is completed. Unused I/Os are disabled with a weak
pull-down resistor. After power-on and before configuration is
completed, these pins are either pulled up or left floating
according to the Mode pin values. See the DC and Switching
Characteristics module for power-on characteristics.
Pin Definitions (Continued)
Pad Name
Dedicated
Pin
Direction
Description
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相關代理商/技術參數(shù)
參數(shù)描述
XC2S150E-6FTG256C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S150E-6FTG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S150E-6PQ208C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family
XC2S150E-6PQ208C0818 制造商:Xilinx 功能描述:
XC2S150E-6PQ208I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family
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