參數(shù)資料
型號(hào)： XC2S150E-6FT256I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 25/108頁(yè)
文件大小： 0K
描述： SPARTAN FPGA 150000 GATE 1.8V
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-IIE
LAB/CLB數(shù)： 864
邏輯元件/單元數(shù)： 3888
RAM 位總計(jì)： 49152
輸入/輸出數(shù)： 182
門(mén)數(shù)： 150000
電源電壓： 1.71 V ~ 1.89 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
其它名稱(chēng)： Q1280323
DS077-2 (v3.0) August 9, 2013
23
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low.
Delaying Configuration
At this time, the user can delay configuration by holding
either PROGRAM or INIT Low, which causes the device to
remain in the memory clearing phase. Note that the bidirec-
tional INIT line is driving a Low logic level during memory
clearing. Thus, to avoid contention, use an open-drain driver
to keep INIT Low.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the con-
figuration data are discussed in the sections treating the
configuration modes individually. The sequence of opera-
tions necessary to load configuration data using the serial
modes is shown in Figure 18. Loading data using the Slave
Parallel mode is shown in Figure 21, page 28.
CRC Error Checking
After the loading of configuration data, a CRC value embed-
ded in the configuration file is checked against a CRC value
calculated within the FPGA. If the CRC values do not
match, the FPGA drives INIT Low to indicate that an error
has occurred and configuration is aborted. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See Clearing Con-
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the config-
uration data, initiates the sequence.
Figure 16: Configuration Flow Diagram
FPGA Drives
INIT Low
Abort Start-up
User Holding
INIT
Low?
User Holding
PROGRAM
Low?
FPGA
Drives INIT
and DONE Low
Load
Configuration
Data Frames
User Operation
Configuration
at Power-up
DS001_11_111501
No
CRC
Correct?
Yes
FPGA
Samples
Mode Pins
Delay
Configuration
Delay
Configuration
Clear
Configuration
Memory
User Pulls
PROGRAM
Low
Start-up Sequence
FPGA Drives DONE High,
Activates I/Os,
Releases GSR net
Yes
No
Yes
No
Yes
Configuration During
User Operation
VCCO
AND
VCCINT
High?
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