- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4285 > XC2S150E-6FT256I (Xilinx Inc)SPARTAN FPGA 150000 GATE 1.8V PDF資料下載
參數(shù)資料
| 型號： | XC2S150E-6FT256I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 24/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN FPGA 150000 GATE 1.8V |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 90 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 864 |
| 邏輯元件/單元數(shù)： | 3888 |
| RAM 位總計： | 49152 |
| 輸入/輸出數(shù)： | 182 |
| 門數(shù)： | 150000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 其它名稱： | Q1280323 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
22
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Signals
There are two kinds of pins that are used to configure
Spartan-IIE devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an input.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a VCCO of 3.3V to drive
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
For a more detailed description than that given below, see
the Spartan-II and Spartan-IIE FPGA Families.
The Process
The sequence of steps necessary to configure Spartan-IIE
devices are shown in Figure 16. The overall flow can be
divided into three different phases.
Initiating configuration
Configuration memory clear
Loading data frames
Start-up
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
Initiating Configuration
There are two different ways to initiate the configuration pro-
cess: applying power to the device or asserting the PRO-
GRAM input.
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
Before configuration can begin, VCCO Bank 2 must be
greater than 1.0V. Furthermore, all VCCINT power pins must
be connected to a 1.8V supply. For more information on
delaying configuration, see Clearing Configuration Memory,
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process by
driving DONE Low, then enters the memory-clearing phase.
Table 11: Configuration Modes
Configuration Mode
Preconfiguration
Pull-ups
M0
M1
M2
CCLK
Direction
Data Width
Serial DOUT
Master Serial mode
No
0
Out
1
Yes
0
1
Slave Parallel mode
(SelectMAP)
Yes
0
1
0
In
8
No
0
1
Boundary-Scan mode
Yes
1
0
N/A
1
No
1
0
1
Slave Serial mode
Yes
1
0
In
1
Yes
No
1
Notes:
1.
During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration
(see Answer 10504).
2.
If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine
whether the unused I/Os have a pull-up, pull-down, or no resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XA3S250E-4PQG208I | IC FPGA SPARTAN-3E 250K 208-PQFP |
| XA3S400-4PQG208I | IC FPGA SPARTAN-3 400K 208-PQFP |
| XC3S250E-4FT256I | IC FPGA SPARTAN 3E 256FTBGA |
| 93LC76BT-I/ST | IC EEPROM 8KBIT 512X16 8-TSSOP |
| 93LC76BT-I/MS | IC EEPROM 8KBIT 512X16 8-MSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S150E-6FTG256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S150E-6FTG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S150E-6PQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S150E-6PQ208C0818 | 制造商:Xilinx 功能描述: |
| XC2S150E-6PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。