參數(shù)資料
型號(hào)： XC2S150E-6FT256I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 14/108頁(yè)
文件大?。?/td> 0K
描述： SPARTAN FPGA 150000 GATE 1.8V
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-IIE
LAB/CLB數(shù)： 864
邏輯元件/單元數(shù)： 3888
RAM 位總計(jì)： 49152
輸入/輸出數(shù)： 182
門(mén)數(shù)： 150000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
其它名稱： Q1280323
DS077-2 (v3.0) August 9, 2013
13
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Configurable Logic Block
The basic building block of the Spartan-IIE FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. The output from the func-
tion generator in each LC drives the CLB output or the
D input of the flip-flop. Each Spartan-IIE FPGA CLB con-
tains four LCs, organized in two similar slices; a single slice
is shown in Figure 6.
In addition to the four basic LCs, the Spartan-IIE FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-IIE FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit syn-
chronous RAM. Furthermore, the two LUTs within a slice
can be combined to create a 16 x 2-bit or 32 x 1-bit syn-
chronous RAM, or a 16 x 1-bit dual-port synchronous RAM.
The Spartan-IIE FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in applica-
tions such as Digital Signal Processing.
Storage Elements
Storage elements in the Spartan-IIE FPGA slice can be
configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
function generators within the slice or directly from slice
inputs, bypassing the function generators.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals may be configured to
operate asynchronously.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
相關(guān)PDF資料
PDF描述
XA3S250E-4PQG208I IC FPGA SPARTAN-3E 250K 208-PQFP
XA3S400-4PQG208I IC FPGA SPARTAN-3 400K 208-PQFP
XC3S250E-4FT256I IC FPGA SPARTAN 3E 256FTBGA
93LC76BT-I/ST IC EEPROM 8KBIT 512X16 8-TSSOP
93LC76BT-I/MS IC EEPROM 8KBIT 512X16 8-MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S150E-6FTG256C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S150E-6FTG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S150E-6PQ208C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family
XC2S150E-6PQ208C0818 制造商:Xilinx 功能描述:
XC2S150E-6PQ208I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*