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參數(shù)資料
| 型號： | UPD72042 |
| 廠商： | NEC Corp. |
| 英文描述： | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
| 中文描述： | LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制 |
| 文件頁數(shù)： | 24/92頁 |
| 文件大?。?/td> | 373K |
| 代理商： | UPD72042 |
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μ
PD72042
24
Data Sheet S14870EJ1V0DS00
(2) Data read mode
When the C/D pin is set low after register read is selected in control mode, the data read mode is set. In data
read mode, the data in a read register is read on the SO pin upon detecting the falling edge of the SCK pin.
Caution When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore, the
remaining bits of the byte cannot be read; at the next falling edge, read is performed starting from
the next byte in the case of RBF, or from the first bit for other registers.
C/D
SCK
SI
A3
A2
A1
A0
×
×
×
D7 D6
D5 D4
D3 D2
D1 D0
SO
State
Control mode
(selection of register read)
Data read mode
Serial clock counter
reset pointer
1
“1”
(3) Data write mode
When the C/D pin is set low after register write has been selected in control mode, data write mode is set. In
data write mode, data for a write register is applied to the SI pin at the rising edge of the SCK pin.
C/D
SCK
SI
A3
A2
A1
A0
×
×
×
D7 D6
D5 D4
D3 D2
D1 D0
SO
0
State
Control mode
(selection of register write)
Data write mode
Serial clock counter
reset pointer
“1”
Caution Register overwrite is started immediately after the eighth clock rising edge. All registers other
than TBF are overwritten on the eighth clock rising edge. (Data of less than eight clock periods
is ignored.)
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