參數(shù)資料
型號(hào): UPD72042
廠商: NEC Corp.
英文描述: LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
中文描述: LSI器件間設(shè)備BusTM(IEBusTM)協(xié)議控制
文件頁(yè)數(shù): 20/92頁(yè)
文件大小: 373K
代理商: UPD72042
μ
PD72042
20
Data Sheet S14870EJ1V0DS00
(3) Reading a lock address (control bits: 4H, 5H)
When a lock address read operation (4H, 5H) is specified, the address (12 bits) of the master unit that
issued the lock instruction is read in one-byte form, as shown below.
Fig. 2-3 Lock Address Format
(4) Locking and unlocking (control bits: Locking (3H, AH, BH), unlocking (6H))
The lock function is used to enable the transfer a message using more than one communication frame.
When locked, a unit cannot receive data from other than the unit that requested the lock.
Locking and unlocking are performed as follows:
1
Locking
The master unit can lock the slave unit by specifying the lock with the corresponding control bits (3H, AH,
BH). In this case, when the transmission or reception of acknowledge bit 0 for the data-length field has been
completed, but the communication frame is then terminated before transmission or reception of as many data
bytes as are specified by the data-length bits is completed, the slave unit is locked. At this time, the bit
indicating the lock status (bit 2) in the slave status byte is set to 1.
2
Unlocking
The master unit can unlock a locked slave unit when the control bits specify locking (3H, AH, or BH) or
unlocking (6H). The slave unit is unlocked once as many data bytes as are specified by the data-length bits
have been transmitted or received within one communication frame. At this time, the bit indicating the lock
status (bit 2) in the slave status byte is reset to 0.
For broadcast, locking or unlocking is not performed.
Caution When a locked unit is to be unlocked by the unit itself, hardware reset or software reset must
be performed. (The lock status can be checked by referring to the contents of the LOR2 register.)
MSB
LSB
Control bits : 4H
Control bits : 5H
Low-order 8 bits
Undefined
High-order 4 bits
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