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參數(shù)資料
| 型號： | TVP5041PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 62/106頁 |
| 文件大小： | 501K |
| 代理商： | TVP5041PFP |
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2–43
2.12 Internal Control Registers
The TVP5041 is initialized and controlled by a set of internal registers which set all the device operating parameters.
Communication between the external controller and TVP5041 is through a standard host port interface. Table 2–14
shows the summary of these registers. The reserved bits must be written with 0. The detailed programming
information of each register is described in the following sections.
NOTE:
In general, the registers residing in the address space 00 through 8F for the I2C and PHI host
interface modes, and 0100 through 018F for the VIP host interface mode can be accessed only
after the microcode has been down loaded to TVP5041s internal program RAM and a
CLEAR-RESET operation has been issued to the internal microprocessor. The only exceptions
are the registers involved in the microcode down load, read back, and CLEAR-RESET
operations. These registers are at addresses 7E, 8E, and 7F respectively for the I2C and PHI
host interface modes and at 017F (CLEAR-RESET operation only) for the VIP host interface
mode. (Note that for the VIP host interface mode the program RAM write and read FIFOs are
mapped to addresses 1500 and 1600 respectively.)
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