參數(shù)資料
型號(hào)： TVP5041PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁數(shù)： 103/106頁
文件大?。?/td> 501K
代理商： TVP5041PFP
3–2
3.3.2
Analog Processing and A/D Converters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Zi
Input impedance, analog video inputs
By design
200
k
Ci
Input capacitance, analog Video inputs
By design
10
pF
Vi(pp)
Input voltage range
Ccoupling = 0.1 F
0.50
1
1.41
V
G
Gain control range
– 5
5
dB
DNL
DC differential nonlinearity
A/D only
0.75
1
LSB
Frequency response
Multiburst (60 IRE)
–0.9
–3
dB
Crosstalk
6 MHz
–50
dB
Noise spectrum
Luminance ramp (100 kHz full; tilt-null)
– 57
dB
Differential phase
Modulated ramp
0.7
°(pk-pk)
Differential gain
Modulated ramp
0.5%
3.4
Timing
3.4.1
Clocks, Video Data, and Sync Timing
PARAMETER
TEST CONDITIONS
(see NOTE 2)
MIN
TYP
MAX
UNIT
Duty cycle PCLK, SCLK
40%
50%
60%
tr(1)
Rise time SCLK
10% to 90%
3
ns
tf(1)
Fall time SCLK
90% to 10%
2
ns
tr(2)
Rise time PCLK
10% to 90%
3
ns
tf(2)
Fall time PCLK
90% to 10%
2
ns
td(8)
Delay time, SCLK rising edge to PREF
5
ns
td(9)
Delay time, SCLK falling edge to PCLK
See Note 3
–2
3
ns
td(10)
Delay time, SCLK falling edge to digital outputs except PCLK,
PREF
See Note 3
–2
10
ns
NOTES:
2. CL = 50 pF
3. SCLK falling edge may occur up to 2 ns after PREF, Y, UV output transition.
SCLK
PREF
PCLK
Y, UV, AVID, HSYN,
VSYN, PALI, FID,
tr(1)
tf(1)
2.6 V
0.6 V
td(8)
td(9)
2.4 V
0.4 V
td(10)
tf(2)
tr(2)
Figure 3–1. Clocks, Video Data, and Sync Timing
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