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參數(shù)資料
| 型號： | TVP5041PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 50/106頁 |
| 文件大小： | 501K |
| 代理商： | TVP5041PFP |
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2–32
2.8.5
VIP Microcode Write Operation (FIFO B)
A microcode write operation is required to download microcode to the TVP5041 program RAM after power-up reset.
During the write cycle, the internal microprocessors program counter resets and points to location zero in the program
RAM and remains reset. Upon completion of the write operation, a microprocessor CLEAR-RESET operation is
required. This is performed by writing into the 017F register to clear reset and resume the microprocessor function.
(There is no specific data requirement to be written into the 017F register; any data resumes the microprocessor
function.)
COMMAND PHASE
DATA PHASE (toTVP5041)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Microcode write
0
1
0
1
0
1
0
1
D
Program RAM FIFO for write
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (to TVP5041)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Clear reset
0
1
0
1
0
1
D
There is no address phase associated with writing to the program RAM.
2.8.6
VIP Microcode Read Operation (FIFO C)
The data written during the microcode write operation can be read from the TVP5041 program RAM. During the read
cycle, the internal microprocessors program counter resets and points to location zero in the program RAM and
remains reset. Upon completion of the read operation, a microprocessor CLEAR-RESET operation is required. This
is performed by writing into the 017F register to clear reset and resume the microprocessor function. (There is no
specific data requirement to be written into the 017F register; any data resumes the microprocessor function.)
COMMAND PHASE
DATA PHASE (from TVP5041)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Microcode read
0
1
0
1
0
D
Program RAM FIFO for Read
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (from TVP5041)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Clear reset
0
1
0
1
0
1
D
There is no address phase associated with reading the program RAM.
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