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參數(shù)資料
| 型號(hào)： | TVP5041PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 44/106頁 |
| 文件大?。?/td> | 501K |
| 代理商： | TVP5041PFP |
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2–26
Table 2–5. VIP Host Port Phase Description
PHASE
EXPLANATION
Command
All host port transfers start with a command phase. The 8-bit command/address byte is multiplexed onto VC0 and VC1 (HAD[1:0])
during the command phase. The command byte selects between devices, read, and write cycles, register or FIFO transfers and
contains the most significant four bits of the register address.
Address
During register transfers the command phase is followed by the address extension phase. The least significant 8-bits of the VIP
register address are multiplexed onto VC0 and VC1 (HAD[1:0]) during the address extension phase. This phase is not present
during FIFO transfers.
Decode
Following the command or command/address phase(s), a one clock delay is required to allow slave devices to decode the address
and determine if they are able to respond within the 1 wait phase requirement for active operation.
Retry
The four clock cycles immediately following the decode phase constitute the retry phase. During the retry phase, the slave indicates
its desire to terminate the operation without transferring any data (retry), add a wait phase or transfer the first byte of data. When the
slave asserts VSTOP, the transfer ends with the retry phase. When the slave neither terminates the transfer nor accepts the byte,
the retry phase is followed by a wait phase.
Wait
During the second cycle of a decode, retry or wait phase, the slave indicates its ability to transfer the next byte of data by driving VC2
(HCTL) low. When the slave does not drive VC2 (HCTL) low and the transfer is not terminated, the current phase is followed by a wait
phase. During wait phases, the current owner (master for writes, slave for reads) continues to drive the HAD bus however no data is
transferred. the slave is allowed to add one wait phase per byte to register accesses without compromising system timing.
Additional wait phases are not prevented but overall system reliability may be compromised.
Data
When VC2 (HCTL) is deasserted during cycle 1 of a retry, wait or data phase, the current phase is followed by a data phase. Data is
transferred between master and slave devices during data phases, multiplexed onto VC0 and VC1 (HAD[1:0]).
TA
Immediately following the last transfer phase of a read transfer, a one cycle delay is required giving the slave time to 3-state the VC0
and VC1 (HAD) bus. The master is free to begin a new bus transfer, driving VC0 and VC1 (HAD) and VC2 (HCTL) immediately
following the TA phase.
2.8.3
VIP Commands and Address Space
Table 2–6 summarizes the supported VIP commands and the address space mapping. Note that only three of the
four VIP FIFO DMA channels are used by TVP5041. The VBI data FIFO is mapped to FIFO A, the program memory
for write operation is mapped to FIFO B, and the program memory for read operation is mapped to FIFO C. FIFO D
is not used by TVP5041 and therefore is indicated as not present in the VIP status 1 register.
Table 2–6. Summary of VIP Commands and Address Spaces
COMMAND
Cmd/Addr
REGISTER ADDRESS
DATA
COMMENT
[7:4]
[3:0]
[7:0]
01
0/1
0
0000
00000000 through 11111111
dddddddd
VIP configuration registers
01
0/1
0
0001
00000000 through 11111111
dddddddd
General TVP5041 registers
01
1
0
0010
00000000 through 11111111
xxxxxxxx
No latency read access 1 phase
01
1
0
0011
Address as previously written
ddddddd
No latency read access 2 phase
01
1
0000
No address phase
xx0/1xxx0/1
FIFO status 0 read
01
1
0001
No address phase
xxxxxx11
FIFO status 1 read
01
1
0100
No address phase
dddddddd
FIFO VBI data read (FIFO A)
01
0
1
0101
No address phase
dddddddd
FIFO program memory write (FIFO B)
01
1
0110
No address phase
dddddddd
FIFO program memory read (FIFO C)
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