參數(shù)資料
型號(hào)： TVP5041PFP
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 45/106頁(yè)
文件大小： 501K
代理商： TVP5041PFP
2–27
2.8.4
Command Byte
During the command phase, the hardware control line(VC2) transitions high and the hardware address lines (VC0
and VC1) transmit the command byte from the host to the TVP5041. The command byte determines the nature of
the data transfer and the TVP5041 address space which is affected.
7
6
5
4
3
2
1
0
Command
DEVSEL1 (0)
DEVSEL0 (1)
R/W
F/R
A11
A10
A9
A8
NAME
DESCRIPTION
DEVSEL1:0
Device select. Always 01 for TVP5041
R/W
1=Read
0=Write
F/R
1=FIFO
0=Register access
A11:8
Address bus upper 4 bits
For register accesses:
0000 = VIP-specific configuration registers
0001 = General TVP5041 registers
0010 = No latency read access phase 1
0011 = No latency read access phase 2
For FIFO accesses:
0000 = FIFO status 0
0001 = FIFO status 1
0100 = VBI FIFO
0101 = Program memory write FIFO
0110 = Program memory read FIFO
2.8.4.1 Access Latency and Wait States
VIP accesses to registers or the VBI FIFO may require the TVP5041 to insert one or more wait states into the access
sequence. For register accesses the wait states may total up to 64
s. All normal writes release the host port
immediately but internal wait states continue to be generated until the operation completes. Any attempt to access
the host port while the write operation has not completed results in slave termination by the TVP5041. For burst writes,
the TVP5041 inserts wait states that may total up to 64
s. Reads (except for no-latency reads detailed in section
2.8.4.2) hold the host port until completion. Figure 2–29 through Figure 2–32 illustrate examples of VIP accesses with
wait states and slave termination by the TVP5041.
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