參數(shù)資料
型號: TVP5041PFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁數(shù): 55/106頁
文件大小: 501K
代理商: TVP5041PFP
2–36
2.8.9
Parallel Host Interface C
The terminal descriptions are defined in Table 2–9.
Table 2–9. Parallel Host Interface C Terminal Description
TERMINAL
SIGNAL
TYPE
DESCRIPTION
A[1:0]
HA[1:0]
I
Address bus from host
D[7:0]
HD[7:0]
I/O
Bidirectional data bus
VC3
CS
I
Chip select, active low
VC2
DS
I
Data strobe, active low
VC1
RD/WR
I
Read, active high—Write, active low
VC0
RDY
O
Ready, active high
INTREQ
O
Interrupt request,
active
low
and
open
drain
by
default,
an
external
pullup
resistor
is
required—can be configured as a conventional CMOS buffer, active high with no external pullup resistor.
Parallel host interface C timing is shown in Figure 2–35. The cycle is initiated by the host when VC2-DS transitions
low. The TVP5041 responds by pulling VC0-RDY low. The TVP5041 will then set VC0-RDY to high impedance, a
pullup resistor is required to indicate the data was received or that the requested data is present on the bus. The host
then completes the cycle by pulling VC2-DS high.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu(6)
A[1:0],D[7:0], RD/WR, CS setup until DS low
5
ns
th(6)
A[1:0],D[7:0], RD/WR, CS hold after DS high
0
ns
td(7)
Delay RDY low after DS low
2
ns
tsu(7)
(Read cycle) D[7:0] setup until RDY high
20
ns
th(7)
(Read cycle) D[7:0] hold after DS high
0
ns
A[1:0]
D[7:0] WRITE
RD/WR (VC1)
DS (VC2)
RDY (VC0)
D[7:0] READ
Write Data
tsu(6)
td(7)
tsu(7)
CS (VC3)
Read Data
th(6)
th(7)
Figure 2–35. Parallel Host Interface C Timing
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