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參數(shù)資料
| 型號(hào)： | TSC2302IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 70/85頁 |
| 文件大小： | 1483K |
| 代理商： | TSC2302IRGZRG4 |
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TSC2302
SLAS394 – JULY 2003
Bit [15:3] — RESERVED
These bits are reserved, and should be written to a default value.
Bit 2 — MONS
Mono Select. This bit determines the position of the mono multiplexer. This multiplexer allows either the left
channel ADC Input or the mono mix of the stereo headphone outputs to be played out of the differential mono
output (MONO+/-).
Table 38. Mono Select
MONS
DESCRIPTION
0
Mono output comes from left ADC input (default).
1
Mono output comes from mono mix of headphone outputs.
Bit 1 — SSRTE
Volume Soft-stepping Rate Select. This bit selects the speed of the soft-stepping function of the TSC2302
volume controls. At normal speed, the actual volume is updated approximately once every 20 s. At half speed,
the actual volume is updated approximately once every 40 s.
Table 39. Volume Soft-Stepping Rate Select
SSRTE
DESCRIPTION
0
Normal step rate used (default).
1
Half step rate used.
Bit 0 — SSTEP
Soft-step Flag. This read-only bit indicates that the TSC2302 volume control soft-stepping is completed.
Table 40. Soft-Step Flag
SSTEP
DESCRIPTION
0
Soft-stepping is not complete
1
Soft-stepping is complete (default)
AUDIO POWER CONTROL REGISTER (Page 2, Address 05H)
The audio power / miscellaneous control register of the TSC2302 controls the powering down of various audio
blocks of the TSC2302. The default state of the TSC2302 has all audio blocks powered down. Before using any
of the audio blocks, they must be powered up by writing to this register. This register also controls the crystal
oscillator clock and buffer, the bass-boost filter, and the de-emphasis filter.
The audio power / miscellaneous control register is formatted as follows:
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
LSB
APD
AVPD
ABPD
HAPD
MOPD
DAPD
ADPD
PDSTS
MIBPD
OSCC
BCKC
SMPD
OTSYN
BASS
DEEMP
L
R
For bits 15 through 8 of this register, writing a 1 to a selected bit powers down the affected section, writing a 0
powers up the section.
Bit 15 — APD
Audio Power Down. This bit powers down the entire audio section if set, regardless of the settings of the other
bits in this register. When this bit is cleared, the individual sections of the audio codec still need to be powered
up individually. The settings of the other bits in the register are retained when this bit is set and cleared. The
default is 1 (powered down).
72
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