參數(shù)資料
型號(hào): TSB14C01AM
廠商: Texas Instruments, Inc.
英文描述: 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
中文描述: 5V的電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995背板收發(fā)器/仲裁者
文件頁(yè)數(shù): 19/31頁(yè)
文件大?。?/td> 424K
代理商: TSB14C01AM
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
definition of logic states
Drivers assert the bus to indicate a 1 logic state, or release the bus to indicate a 0 logic state. To assert the bus,
a driver sinks current. To release the bus, drivers are asserted to a high-impedance state or turned off, allowing
the bus signal to be pulled to the termination voltage of the bus.
NOTE
This typically results in a logical inversion of signals on TTL and BTL buses. Signals on ECL buses
typically are not inverted.
All drivers operate in a wired-ORed or open-collector mode during arbitration. Drivers can operate in a totem
pole mode during data packet and acknowledge transfers. In this mode, a driver can drive the bus into its
released state in order to decrease the rise time of the bus signal (referred to as a rescinding release with TTL
technology).
bit rates
Data transmission and reception occurs at 49.152 Mbit/s or 98.304 Mbit/s (
±
100 ppm). Regardless of the
interface technology, arbitration occurs at an arbitration clock rate of 49.152 MHz.
backplane transmit data timing
Edge separation is the minimum required time between any two consecutive transitions of the backplane bus
signals, as they appear from the output of the transmitters, whether they be transitions on the same signal or
transitions on the two separate signals. A minimum edge separation is required to ensure proper operation of
the data strobe bit-level encoding mechanism. TDATA and TSTRB have the relationship shown in Figure 9 and
Table 13.
t1
t1
t1
t1
t2
t2
t2
t2
TDATA
TSTRB
Figure 9. Minimum Edge Separation
Table 13. TSB14C01A to Backplane Transceiver Timing
ááááááááááá
ááááááááááááááááááá
áááááááááá
áááááá
ááááááááááá
ááááááááááá
ááááááá
áááááááááááááááááááá
相關(guān)PDF資料
PDF描述
TSSOP-56 Fairchild Semiconductor Product Package Material Disclosure
TSSOP-8PIN Package Dimensions
TSWC01622 SONET/SDH/PDH/ATM Clock Synthesizer and Protection Switch(SONET/SDH/PDH/ATM 時(shí)鐘合成器和保護(hù)開(kāi)關(guān))
TTB28F400BV-B60 LAMP FILAMENT 14V 16MM
TTB28F200CV-B60 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB14C01AMHV 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
TSB14C01APM 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMG4 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMR 功能描述:1394 接口集成電路 50/100Mbps BACKPLANE Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMRG4 功能描述:1394 接口集成電路 5V 1Port 50/100Mbps BP Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray