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| 型號： | TSB14C01AM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的電機及電子學(xué)工程師聯(lián)合會1394-1995背板收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 11/31頁 |
| 文件大小： | 424K |
| 代理商： | TSB14C01AM |
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TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The TSB14C01A (phy) is designed to operate with a link such as the Texas Instruments TSB12C01A. These
devices use an interface such as described in Annex J of the IEEE 1394-1995 standard. Details of how the
TSB12C01A device operates are given in the TSB12C01A data manual (literature number SLLS219). For
information on the operation of 1394, see the IEEE 1394-1995 standard. For more specific information on the
backplane phy, see the following sections of IEEE 1394-1995 standard: Chapter 5, Backplane physical layer
specification Annex D, Backplane physical ayer timing Annex F, Backplane physical mplementation example
Annex G, Backplane isochronous resource manager selection The following paragraphs describe the
operation of the phy-link interface.
The TSB14C01A supports 100 Mbit/s data transfers and has two bidirectional data lines (D0 and D1) crossing
the interface. In addition there are two bidirectional control lines (CTL0 and CTL1), the SCLK line from the phy
to the link, and the link request line (LREQ) from the link to the phy. The TSB14C01A phy has control of all the
bidirectional terminals. The link is allowed to drive these terminals only after it has been given permission by
the phy. The dedicated LREQ request terminal is used by the link for any activity that it can initiate.
There are four basic operations that can occur in the interface: request, status, transmit, and receive. All
operations but request are initiated by the phy. The link uses the request operation to read or write an internal
phy register or to ask the phy to initiate a transmit action. The phy initiates a receive action whenever a packet
is received from the serial bus.
When the phy has control of the bus, the CTL0 and CTL1 lines are encoded as shown in Table 4.
Table 4. CTL0 and CTL1 Control Lines When the Phy Has Control
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1
1
1
Transmit
The link has been given control of the bus to send an outgoing packet.
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0
Idle
No activity is occurring (this is the default mode).
0
Receive
An incoming packet is being sent from the phy to the link.
When the link has control of the bus (only with phy permission) the CTL0 and CTL1 lines are encoded as shown
in Table 5.
Table 5. CTL0 and CTL1 Control Lines When the Link Has Control
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When the link needs to request the bus or access a register that is located in the TSB14C01A phy, a serial stream
of information is sent across the LREQ line. The length of the stream varies depending on whether the transfer
is a bus request, a read command, or a write command (see Table 6). Regardless of the type of transfer, a start
bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0
is the MSB, and is transmitted first. The LREQ line is required to idle low (logic level 0).
CTL0
CTL1
Name
Description of Activity
0
0
1
0
Idle
The link releases the bus (the transmission has been completed).
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| TSB14C01AMHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB14C01APM | 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01APMG4 | 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01APMR | 功能描述:1394 接口集成電路 50/100Mbps BACKPLANE Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01APMRG4 | 功能描述:1394 接口集成電路 5V 1Port 50/100Mbps BP Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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