參數(shù)資料
型號(hào)： TSB14C01AM
廠商： Texas Instruments, Inc.
英文描述： 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
中文描述： 5V的電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995背板收發(fā)器/仲裁者
文件頁(yè)數(shù)： 15/31頁(yè)
文件大?。?/td> 424K
代理商： TSB14C01AM
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
status
When the phy has status information to transfer to the link, it initiates a status transfer. The phy waits until the
interface is idle to perform the transfer. The phy initiates the transfer by asserting status (01) on the CTL
terminals, along with the first two bits of status information on D0 and D1. The phy maintains CTL == status for
the duration of the status transfer. The phy can temporarily halt a status transfer by asserting something other
than status on the CTL terminals. This is done in the event that a packet arrives before the status transfer
completes. There must be at least one idle cycle between consecutive status transfers.
The phy normally sends only the first 4 bits of status to the link. These bits are status flags that are needed by
link state machines. The phy sends an entire status packet to the link after a request transfer that contains a
read request.
The definition of the bits in the status transfer are shown in Table 12 (also see Table 2 and Table 9). The 16-bit
status stream is defined in Table 12.
ááááááááááááááááááááááááá
á
áááááááááááááááááááááááá
á
á
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
á
áááááááááááááááááááááááá
ááááááááááááááááááááááááá
Bit(s)
á
Name
á
Description
ááááááááááááááááááááááááá
áá
áá
áá
2
áá
á
ááá
Bus reset
á
ááá
á
link to detect the completion of an isochronous cycle.
arbitration reset gap time (this time is defined in the 1394 standard). This bit
is used by the link in its busy/retry state machine.
á
Indicates that the phy has detected that the bus has been idle for an
á
1
á
Indicates that the phy has entered the bus reset state.
ááá
á
Indicates that the phy has detected that the bus has been idle for a subaction
gap time (this time is defined in the 1394 standard). This bit is used by the
3
Reserved
Reserved
4-7
á
á
Holds the address of the phy register whose contents are transferred to the
00
01
01
01
00
00
Phy
CTL0, CTL1
00
S[0,1]
00
00
Phy
D0, D1
S[14,15]
S[2,3]
00
00
Figure 5. Status Transfer Timing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB14C01AMHV 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
TSB14C01APM 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMG4 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMR 功能描述:1394 接口集成電路 50/100Mbps BACKPLANE Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB14C01APMRG4 功能描述:1394 接口集成電路 5V 1Port 50/100Mbps BP Phy Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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