參數(shù)資料
型號: TSB14C01AM
廠商: Texas Instruments, Inc.
英文描述: 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
中文描述: 5V的電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995背板收發(fā)器/仲裁者
文件頁數(shù): 17/31頁
文件大?。?/td> 424K
代理商: TSB14C01AM
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
transmit timing
11
00
ZZ
ZZ
ZZ
ZZ
Phy
CTL0, CTL1
ZZ
ZZ
00
ZZ
ZZ
00
00
00
ZZ
ZZ
ZZ
ZZ
Phy
D0, D1
ZZ
ZZ
00
ZZ
ZZ
00
ZZ
ZZ
01
10
10
10
Link
CTL0, CTL1
00
00
ZZ
01
10
ZZ
ZZ
ZZ
00
D0
D1
D2
Link
D0, D1
00
00
ZZ
00
Dn
ZZ
Single Packet
ZZ
ZZ
00
11
00
ZZ
Phy
CTL0, CTL1
ZZ
ZZ
ZZ
00
ZZ
Continued Packet
ZZ
ZZ
ZZ
00
00
00
ZZ
Phy
D0, D1
ZZ
ZZ
ZZ
00
ZZ
ZZ
01
00
ZZ
ZZ
ZZ
01
Link
CTL0, CTL1
01
10
10
ZZ
10
10
00
00
ZZ
ZZ
ZZ
00
Link
D0, D1
00
D0
D1
ZZ
Dn
Dn-1
NOTE A: ZZ = High Impedance State
D0 = > Dn = Packet data
Figure 6. Transmit Timing
receive
When data is received by the phy from the serial bus, it transfers the data to the link for further processing. The
phy asserts receive (see Table 4) on the CTL lines and asserts each D terminal high. The phy indicates the start
of the packet by placing the speed code on the data bus. The phy then proceeds with the transmittal of the packet
to the link on the D lines while still keeping the receive status on the CTL terminals. Once the packet has been
completely transferred, the phy asserts idle on the CTL terminals, which completes the receive operation (see
Figure 7).
NOTE
The speed code is a phy-link protocol and is not included in the CRC.
10
10
10
10
Phy
CTL0, CTL1
10
00
00
10
00
11
SPD
D0
D1
Phy
D0, D1
Dn
00
00
11
00
NOTE A: SPD = Speed Code (For the backplane, this speed is fixed at D0, D1 = 00).
D0 to Dn = Packet data
Figure 7. Receive Timing
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參數(shù)描述
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