參數(shù)資料
型號: TSB14C01AM
廠商: Texas Instruments, Inc.
英文描述: 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
中文描述: 5V的電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995背板收發(fā)器/仲裁者
文件頁數(shù): 12/31頁
文件大小: 424K
代理商: TSB14C01AM
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 6. Request Bit Length
ááááááááááá
á
ááááááááááá
Read register request
ááááááááááá
áááááá
á
Bits
ááá
11
17
á
ááááááááááá
Bus request (backplane)
ááááááááááá
Write register request
9
For a bus request in the cable environment, the length of the LREQ data stream is 7 bits as shown in Table 7.
Table 7. Bus Request For Cable Environment
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
á
áááááááááááááááááááááááááá
á
á
áááááááááááááááááááááááááá
When LREQ transfer is a bus request in the backplane environment, it is 11 bits long and has the format shown
in Table 8.
Bit(s)
Start bit
Name
Indicates the beginning of the transfer (always 1).
á
Description
áá
áá
áá
0
á
áááá
áááá
áááá
1-3
Request type
á
ááááááááááááááááá
ááááááááááááááááá
á
á
á
á
á
á
Table 8. Bus Request For Backplane Environment
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
á
áááááááááááááááááááááááááá
ááááááááááááááááááááááááá
á
á
ááááááááááááááááááááááááá
For a Read Register Request the length of the LREQ data stream is 9 bits as shown in Table 9 (also see Table 3
for the bit definitions).
Bit(s)
Stop bit
Name
á
Indicates the end of the transfer (always 0).
Description
áá
0
Start bit
Indicates the beginning of the transfer (always 1).
á
áááá
á
ááááááááááááááááá
á
áá
áá
á
á
áááá
áááá
á
ááááááááááááááááá
ááááááááááááááááá
á
á
10
Table 9. Read Request Format
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
ááááááááááááááááááááááááá
4-7
Is the address of the phy register to be read.
8
Stop bit
Indicates the end of the transfer (always 0).
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